www.pudn.com > shiboqi.rar > AD.v, change:2013-03-18,size:361b


module AD(clk,rst_n,data_in,data_out,clk_out); 
input clk,rst_n; 
input[9:0]data_in; 
output[9:0]data_out; 
output clk_out; 
 
reg[9:0]data_out_r;  
always@(negedge clk or negedge rst_n) 
begin 
	if(!rst_n)data_out_r<=10'd0; 
	else data_out_r<=data_in; 
end 
 
wire[9:0]data_out; 
assign data_out=data_out_r;  
 
wire clk_out; 
assign clk_out=clk; 
endmodule