www.pudn.com > chuankou.rar > rx_module.v, change:2013-05-02,size:1701b


//串口点灯 
module rx_module(clk,rst_n,rx_pin_in,rx_en_sig,rx_done_sig,rx_data); 
input clk,rst_n; 
input rx_pin_in,rx_en_sig; 
output rx_done_sig; 
output[7:0] rx_data; 
//***************检测起始信号******************************** 
reg key1,key2; 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n)  
	begin 
		key1<=1'b0; 
		key2<=1'b0; 
	end 
	else  
	begin 
		key1<=rx_pin_in; 
		key2<=key1; 
	end 
end 
wire start=key2 & !key1; 
//********************波特率设置 N=(1/想要的波特率)/(1/时钟频率)*** 
reg[12:0] count; 
reg bps_clk; 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n)  
	begin 
		count<=13'b0; 
		bps_clk<=1'b0; 
	end 
	else if(count==13'd5208)//9600 
		count<=13'd0; 
	else if(count_sig) 
		count<=count+1'b1; 
	else if(count==13'd2604) 
		bps_clk<=1'b1; 
	else 
	begin 
		count<=13'b0; 
		bps_clk<=1'b0; 
	end 
end 
//****************************************************************** 
reg[3:0] i; 
reg[7:0] rdata; 
reg count_sig; 
reg rx_done_sig; 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n) 
	begin 
		i<=4'd0; 
		rdata<=8'd0; 
		count_sig<=1'b0; 
		rx_done_sig<=1'b0; 
	end 
	else if(rx_en_sig) 
		case(i) 
			4'd0 : 
			if(start)  
			begin 
				i<=i+1'b1; 
				count_sig<=1'b1; 
			end 
			4'd1 : 
			if(bps_clk) i<=i+1'b1; 
			4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9 : 
			if(bps_clk)  
			begin 
				i<=i+1'b1; 
				rdata[i-2]<=rx_pin_in; 
			end 
			4'd10 : 
			if(bps_clk) i<=i+1'b1; 
			4'd11 : 
			if(bps_clk) i<=i+1'b1; 
			4'd12 : 
			begin 
				i<=i+1'b1; 
				count_sig<=1'b0; 
				rx_done_sig<=1'b1; 
			end 
			4'd13 : 
			begin 
				i<=1'b0; 
				rx_done_sig<=1'b0; 
			end 
		endcase 
end 
 
assign rx_data = rdata; 
 
endmodule