www.pudn.com > chuankou.rar > control.v, change:2013-05-01,size:376b


module control(clk,rst_n,rx_en_sig,rx_done_sig,rx_data,led); 
input clk,rst_n; 
input rx_done_sig; 
input[7:0] rx_data; 
output rx_en_sig; 
output[7:0] led; 
 
reg[7:0] led; 
reg  rx_en_sig; 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n) led<=8'd0; 
	else if(rx_done_sig) 
	begin 
		led<=rx_data; 
		rx_en_sig<=1'b0; 
	end 
	else rx_en_sig<=1'b1; 
end 
 
endmodule