www.pudn.com > chuankou.rar > tx_module.v, change:2013-05-02,size:1833b


module tx_module(clk,rst_n,tx_pin_out); 
input clk,rst_n; 
output tx_pin_out; 
//********************波特率设置 N=(1/想要的波特率)/(1/时钟频率)*** 
reg[12:0] count; 
reg bps_clk; 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n)  
	begin 
		count<=13'b0; 
		bps_clk<=1'b0; 
	end 
	else if(count==13'd5208)//9600 
		count<=13'd0; 
	else if(tx_en_sig) 
		count<=count+1'b1; 
	else if(count==13'd2604) 
		bps_clk<=1'b1; 
	else 
	begin 
		count<=13'b0; 
		bps_clk<=1'b0; 
	end 
end 
//****************************************************************** 
reg[3:0] i; 
reg[7:0] tx_data; 
reg tx_pin_out; 
reg tx_done_sig; 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n) 
	begin 
		i<=4'd0; 
		tx_pin_out<=1'b1; 
		tx_done_sig<=1'b0; 
	end 
	else if(tx_en_sig) 
		case(i) 
			4'd0 : 
			if(bps_clk)  
			begin 
				i<=i+1'b1; 
				tx_pin_out<=1'b0; 
			end 
			4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8 : 
			if(bps_clk)  
			begin 
				i<=i+1'b1; 
				tx_pin_out<=1'b1; 
			end 
			4'd9 : 
			if(bps_clk)  
			begin 
				i<=i+1'b1; 
				tx_pin_out<=1'b1; 
			end 
			4'd10 : 
			if(bps_clk)  
			begin 
				i<=i+1'b1; 
				tx_pin_out<=1'b1; 
			end 
			4'd11 : 
			if(bps_clk)  
			begin 
				i<=i+1'b1; 
				tx_done_sig<=1'b1; 
			end 
			4'd12 : 
			begin 
				i<=1'b0; 
				tx_done_sig<=1'b0; 
			end 
		endcase 
end 
//**************控制******************************************* 
reg[25:0] cnt; 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n) cnt<=26'd0; 
	else if(cnt==26'd49999999) 
		cnt<=26'd0; 
	else  
		cnt<=cnt+1'b1; 
end 
reg tx_en_sig; 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n) 
	begin 
		tx_en_sig<=1'b0; 
		tx_data<=8'hfe; 
	end 
	else if(tx_done_sig) 
	begin 
		tx_en_sig<=1'b0; 
		tx_data<=8'hfe; 
	end 
	else if(cnt==26'd49999998) 
		tx_en_sig<=1'b1; 
end 
	 
endmodule