www.pudn.com > chuankou.rar > tx_module.qsf, change:2014-08-09,size:3146b


# -------------------------------------------------------------------------- # 
# 
# Copyright (C) 1991-2010 Altera Corporation 
# Your use of Altera Corporation's design tools, logic functions  
# and other software and tools, and its AMPP partner logic  
# functions, and any output files from any of the foregoing  
# (including device programming or simulation files), and any  
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License  
# Subscription Agreement, Altera MegaCore Function License  
# Agreement, or other applicable license agreement, including,  
# without limitation, that your use is for the sole purpose of  
# programming logic devices manufactured by Altera and sold by  
# Altera or its authorized distributors.  Please refer to the  
# applicable agreement for further details. 
# 
# -------------------------------------------------------------------------- # 
# 
# Quartus II 
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version 
# Date created = 15:50:56  May 01, 2013 
# 
# -------------------------------------------------------------------------- # 
# 
# Notes: 
# 
# 1) The default values for assignments are stored in the file: 
#		tx_module_assignment_defaults.qdf 
#    If this file doesn't exist, see file: 
#		assignment_defaults.qdf 
# 
# 2) Altera recommends that you do not modify this file. This 
#    file is updated automatically by the Quartus II software 
#    and any changes you make may be lost or overwritten. 
# 
# -------------------------------------------------------------------------- # 
 
 
set_global_assignment -name FAMILY "Cyclone IV E" 
set_global_assignment -name DEVICE Auto 
set_global_assignment -name TOP_LEVEL_ENTITY tx_module 
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2" 
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:50:56  MAY 01, 2013" 
set_global_assignment -name LAST_QUARTUS_VERSION 13.1 
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga 
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 
set_global_assignment -name USE_CONFIGURATION_DEVICE ON 
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" 
set_global_assignment -name VERILOG_FILE tx_module.v 
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" 
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" 
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" 
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 
set_location_assignment PIN_L1 -to clk 
set_location_assignment PIN_L2 -to rst_n 
set_location_assignment PIN_R21 -to tx_pin_out 
set_global_assignment -name MISC_FILE "C:/Users/Administrator/Desktop/ģ/ڷ/tx_module.dpf" 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top