www.pudn.com > DS28E01_final.zip > top_level.hier_info, change:2015-01-09,size:87795b


|top_level 
clk_1M <= fenpin:inst2.clk_1M 
Clock_In => fenpin:inst2.CLK 
One_Wire <> SHA1_engine:inst.One_Wire 
out[0] <= count:inst3.q[0] 
out[1] <= count:inst3.q[1] 
out[2] <= count:inst3.q[2] 
out[3] <= count:inst3.q[3] 
out[4] <= count:inst3.q[4] 
out[5] <= count:inst3.q[5] 
out[6] <= count:inst3.q[6] 
out[7] <= count:inst3.q[7] 
 
 
|top_level|fenpin:inst2 
CLK => clk_1M~reg0.CLK 
CLK => cnt[0].CLK 
CLK => cnt[1].CLK 
CLK => cnt[2].CLK 
CLK => cnt[3].CLK 
CLK => cnt[4].CLK 
CLK => cnt[5].CLK 
clk_1M <= clk_1M~reg0.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|top_level|SHA1_engine:inst 
Enable <= small_micro_32:inst4.Enable 
Resetn_In => small_micro_32:inst4.resetn 
Resetn_In => One_Wire:inst.resetn 
Clock_In => small_micro_32:inst4.clock 
Clock_In => One_Wire:inst.clock 
Clock_In => RNG_8Bits:inst2.clock 
One_Wire <> One_Wire:inst.One_Wire_data 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4 
resetn => r.T_Counter[0].ACLR 
resetn => r.T_Counter[1].ACLR 
resetn => r.T_Counter[2].ACLR 
resetn => r.T_Counter[3].ACLR 
resetn => r.T_Counter[4].ACLR 
resetn => r.T_Counter[5].ACLR 
resetn => r.T_Counter[6].ACLR 
resetn => r.P_Counter[0].ACLR 
resetn => r.P_Counter[1].ACLR 
resetn => r.P_Counter[2].ACLR 
resetn => r.P_Counter[3].ACLR 
resetn => r.P_Counter[4].ACLR 
resetn => r.P_Counter[5].ACLR 
resetn => r.P_Counter[6].ACLR 
resetn => r.P_Counter[7].ACLR 
resetn => r.Enable_reg[0].ACLR 
resetn => r.Enable_reg[1].ACLR 
resetn => r.Enable_reg[2].ACLR 
resetn => r.Enable_reg[3].ACLR 
resetn => r.Enable_reg[4].ACLR 
resetn => r.Reg3[0].ACLR 
resetn => r.Reg3[1].ACLR 
resetn => r.Reg3[2].ACLR 
resetn => r.Reg3[3].ACLR 
resetn => r.Reg3[4].ACLR 
resetn => r.Reg3[5].ACLR 
resetn => r.Reg3[6].ACLR 
resetn => r.Reg3[7].ACLR 
resetn => r.Reg3[8].ACLR 
resetn => r.Reg3[9].ACLR 
resetn => r.Reg3[10].ACLR 
resetn => r.Reg3[11].ACLR 
resetn => r.Reg3[12].ACLR 
resetn => r.Reg3[13].ACLR 
resetn => r.Reg3[14].ACLR 
resetn => r.Reg3[15].ACLR 
resetn => r.Reg3[16].ACLR 
resetn => r.Reg3[17].ACLR 
resetn => r.Reg3[18].ACLR 
resetn => r.Reg3[19].ACLR 
resetn => r.Reg3[20].ACLR 
resetn => r.Reg3[21].ACLR 
resetn => r.Reg3[22].ACLR 
resetn => r.Reg3[23].ACLR 
resetn => r.Reg3[24].ACLR 
resetn => r.Reg3[25].ACLR 
resetn => r.Reg3[26].ACLR 
resetn => r.Reg3[27].ACLR 
resetn => r.Reg3[28].ACLR 
resetn => r.Reg3[29].ACLR 
resetn => r.Reg3[30].ACLR 
resetn => r.Reg3[31].ACLR 
resetn => r.Reg2[0].ACLR 
resetn => r.Reg2[1].ACLR 
resetn => r.Reg2[2].ACLR 
resetn => r.Reg2[3].ACLR 
resetn => r.Reg2[4].ACLR 
resetn => r.Reg2[5].ACLR 
resetn => r.Reg2[6].ACLR 
resetn => r.Reg2[7].ACLR 
resetn => r.Reg2[8].ACLR 
resetn => r.Reg2[9].ACLR 
resetn => r.Reg2[10].ACLR 
resetn => r.Reg2[11].ACLR 
resetn => r.Reg2[12].ACLR 
resetn => r.Reg2[13].ACLR 
resetn => r.Reg2[14].ACLR 
resetn => r.Reg2[15].ACLR 
resetn => r.Reg2[16].ACLR 
resetn => r.Reg2[17].ACLR 
resetn => r.Reg2[18].ACLR 
resetn => r.Reg2[19].ACLR 
resetn => r.Reg2[20].ACLR 
resetn => r.Reg2[21].ACLR 
resetn => r.Reg2[22].ACLR 
resetn => r.Reg2[23].ACLR 
resetn => r.Reg2[24].ACLR 
resetn => r.Reg2[25].ACLR 
resetn => r.Reg2[26].ACLR 
resetn => r.Reg2[27].ACLR 
resetn => r.Reg2[28].ACLR 
resetn => r.Reg2[29].ACLR 
resetn => r.Reg2[30].ACLR 
resetn => r.Reg2[31].ACLR 
resetn => r.Reg1[0].ACLR 
resetn => r.Reg1[1].ACLR 
resetn => r.Reg1[2].ACLR 
resetn => r.Reg1[3].ACLR 
resetn => r.Reg1[4].ACLR 
resetn => r.Reg1[5].ACLR 
resetn => r.Reg1[6].ACLR 
resetn => r.Reg1[7].ACLR 
resetn => r.Reg1[8].ACLR 
resetn => r.Reg1[9].ACLR 
resetn => r.Reg1[10].ACLR 
resetn => r.Reg1[11].ACLR 
resetn => r.Reg1[12].ACLR 
resetn => r.Reg1[13].ACLR 
resetn => r.Reg1[14].ACLR 
resetn => r.Reg1[15].ACLR 
resetn => r.Reg1[16].ACLR 
resetn => r.Reg1[17].ACLR 
resetn => r.Reg1[18].ACLR 
resetn => r.Reg1[19].ACLR 
resetn => r.Reg1[20].ACLR 
resetn => r.Reg1[21].ACLR 
resetn => r.Reg1[22].ACLR 
resetn => r.Reg1[23].ACLR 
resetn => r.Reg1[24].ACLR 
resetn => r.Reg1[25].ACLR 
resetn => r.Reg1[26].ACLR 
resetn => r.Reg1[27].ACLR 
resetn => r.Reg1[28].ACLR 
resetn => r.Reg1[29].ACLR 
resetn => r.Reg1[30].ACLR 
resetn => r.Reg1[31].ACLR 
resetn => r.Instr_Reg[0].ACLR 
resetn => r.Instr_Reg[1].ACLR 
resetn => r.Instr_Reg[2].ACLR 
resetn => r.Instr_Reg[3].ACLR 
resetn => r.Instr_Reg[4].ACLR 
resetn => r.Instr_Reg[5].ACLR 
resetn => r.Instr_Reg[6].ACLR 
resetn => r.Instr_Reg[7].ACLR 
resetn => r.Instr_Reg[8].ACLR 
resetn => r.Instr_Reg[9].ACLR 
resetn => r.Instr_Reg[10].ACLR 
resetn => r.Instr_Reg[11].ACLR 
resetn => r.Instr_Reg[12].ACLR 
resetn => r.Instr_Reg[13].ACLR 
resetn => r.Instr_Reg[14].ACLR 
resetn => r.Instr_Reg[15].ACLR 
resetn => r.FSM~3.DATAIN 
clock => program_mem:Mem_inst.clock 
clock => r.T_Counter[0].CLK 
clock => r.T_Counter[1].CLK 
clock => r.T_Counter[2].CLK 
clock => r.T_Counter[3].CLK 
clock => r.T_Counter[4].CLK 
clock => r.T_Counter[5].CLK 
clock => r.T_Counter[6].CLK 
clock => r.P_Counter[0].CLK 
clock => r.P_Counter[1].CLK 
clock => r.P_Counter[2].CLK 
clock => r.P_Counter[3].CLK 
clock => r.P_Counter[4].CLK 
clock => r.P_Counter[5].CLK 
clock => r.P_Counter[6].CLK 
clock => r.P_Counter[7].CLK 
clock => r.Enable_reg[0].CLK 
clock => r.Enable_reg[1].CLK 
clock => r.Enable_reg[2].CLK 
clock => r.Enable_reg[3].CLK 
clock => r.Enable_reg[4].CLK 
clock => r.Reg3[0].CLK 
clock => r.Reg3[1].CLK 
clock => r.Reg3[2].CLK 
clock => r.Reg3[3].CLK 
clock => r.Reg3[4].CLK 
clock => r.Reg3[5].CLK 
clock => r.Reg3[6].CLK 
clock => r.Reg3[7].CLK 
clock => r.Reg3[8].CLK 
clock => r.Reg3[9].CLK 
clock => r.Reg3[10].CLK 
clock => r.Reg3[11].CLK 
clock => r.Reg3[12].CLK 
clock => r.Reg3[13].CLK 
clock => r.Reg3[14].CLK 
clock => r.Reg3[15].CLK 
clock => r.Reg3[16].CLK 
clock => r.Reg3[17].CLK 
clock => r.Reg3[18].CLK 
clock => r.Reg3[19].CLK 
clock => r.Reg3[20].CLK 
clock => r.Reg3[21].CLK 
clock => r.Reg3[22].CLK 
clock => r.Reg3[23].CLK 
clock => r.Reg3[24].CLK 
clock => r.Reg3[25].CLK 
clock => r.Reg3[26].CLK 
clock => r.Reg3[27].CLK 
clock => r.Reg3[28].CLK 
clock => r.Reg3[29].CLK 
clock => r.Reg3[30].CLK 
clock => r.Reg3[31].CLK 
clock => r.Reg2[0].CLK 
clock => r.Reg2[1].CLK 
clock => r.Reg2[2].CLK 
clock => r.Reg2[3].CLK 
clock => r.Reg2[4].CLK 
clock => r.Reg2[5].CLK 
clock => r.Reg2[6].CLK 
clock => r.Reg2[7].CLK 
clock => r.Reg2[8].CLK 
clock => r.Reg2[9].CLK 
clock => r.Reg2[10].CLK 
clock => r.Reg2[11].CLK 
clock => r.Reg2[12].CLK 
clock => r.Reg2[13].CLK 
clock => r.Reg2[14].CLK 
clock => r.Reg2[15].CLK 
clock => r.Reg2[16].CLK 
clock => r.Reg2[17].CLK 
clock => r.Reg2[18].CLK 
clock => r.Reg2[19].CLK 
clock => r.Reg2[20].CLK 
clock => r.Reg2[21].CLK 
clock => r.Reg2[22].CLK 
clock => r.Reg2[23].CLK 
clock => r.Reg2[24].CLK 
clock => r.Reg2[25].CLK 
clock => r.Reg2[26].CLK 
clock => r.Reg2[27].CLK 
clock => r.Reg2[28].CLK 
clock => r.Reg2[29].CLK 
clock => r.Reg2[30].CLK 
clock => r.Reg2[31].CLK 
clock => r.Reg1[0].CLK 
clock => r.Reg1[1].CLK 
clock => r.Reg1[2].CLK 
clock => r.Reg1[3].CLK 
clock => r.Reg1[4].CLK 
clock => r.Reg1[5].CLK 
clock => r.Reg1[6].CLK 
clock => r.Reg1[7].CLK 
clock => r.Reg1[8].CLK 
clock => r.Reg1[9].CLK 
clock => r.Reg1[10].CLK 
clock => r.Reg1[11].CLK 
clock => r.Reg1[12].CLK 
clock => r.Reg1[13].CLK 
clock => r.Reg1[14].CLK 
clock => r.Reg1[15].CLK 
clock => r.Reg1[16].CLK 
clock => r.Reg1[17].CLK 
clock => r.Reg1[18].CLK 
clock => r.Reg1[19].CLK 
clock => r.Reg1[20].CLK 
clock => r.Reg1[21].CLK 
clock => r.Reg1[22].CLK 
clock => r.Reg1[23].CLK 
clock => r.Reg1[24].CLK 
clock => r.Reg1[25].CLK 
clock => r.Reg1[26].CLK 
clock => r.Reg1[27].CLK 
clock => r.Reg1[28].CLK 
clock => r.Reg1[29].CLK 
clock => r.Reg1[30].CLK 
clock => r.Reg1[31].CLK 
clock => r.Instr_Reg[0].CLK 
clock => r.Instr_Reg[1].CLK 
clock => r.Instr_Reg[2].CLK 
clock => r.Instr_Reg[3].CLK 
clock => r.Instr_Reg[4].CLK 
clock => r.Instr_Reg[5].CLK 
clock => r.Instr_Reg[6].CLK 
clock => r.Instr_Reg[7].CLK 
clock => r.Instr_Reg[8].CLK 
clock => r.Instr_Reg[9].CLK 
clock => r.Instr_Reg[10].CLK 
clock => r.Instr_Reg[11].CLK 
clock => r.Instr_Reg[12].CLK 
clock => r.Instr_Reg[13].CLK 
clock => r.Instr_Reg[14].CLK 
clock => r.Instr_Reg[15].CLK 
clock => r.FSM~1.DATAIN 
OW_Command[0] <= OW_Command.DB_MAX_OUTPUT_PORT_TYPE 
OW_Command[1] <= OW_Command.DB_MAX_OUTPUT_PORT_TYPE 
OW_Command[2] <= OW_Command.DB_MAX_OUTPUT_PORT_TYPE 
OW_Command[3] <= OW_Command.DB_MAX_OUTPUT_PORT_TYPE 
OW_Write_Byte[0] <= Selector119.DB_MAX_OUTPUT_PORT_TYPE 
OW_Write_Byte[1] <= Selector118.DB_MAX_OUTPUT_PORT_TYPE 
OW_Write_Byte[2] <= Selector117.DB_MAX_OUTPUT_PORT_TYPE 
OW_Write_Byte[3] <= Selector116.DB_MAX_OUTPUT_PORT_TYPE 
OW_Write_Byte[4] <= Selector115.DB_MAX_OUTPUT_PORT_TYPE 
OW_Write_Byte[5] <= Selector114.DB_MAX_OUTPUT_PORT_TYPE 
OW_Write_Byte[6] <= Selector113.DB_MAX_OUTPUT_PORT_TYPE 
OW_Write_Byte[7] <= Selector112.DB_MAX_OUTPUT_PORT_TYPE 
RNG_Byte[0] => Mux57.IN4 
RNG_Byte[0] => Mux65.IN4 
RNG_Byte[0] => Mux73.IN4 
RNG_Byte[1] => Mux56.IN4 
RNG_Byte[1] => Mux64.IN4 
RNG_Byte[1] => Mux72.IN4 
RNG_Byte[2] => Mux55.IN4 
RNG_Byte[2] => Mux63.IN4 
RNG_Byte[2] => Mux71.IN4 
RNG_Byte[3] => Mux54.IN4 
RNG_Byte[3] => Mux62.IN4 
RNG_Byte[3] => Mux70.IN4 
RNG_Byte[4] => Mux53.IN4 
RNG_Byte[4] => Mux61.IN4 
RNG_Byte[4] => Mux69.IN4 
RNG_Byte[5] => Mux52.IN4 
RNG_Byte[5] => Mux60.IN4 
RNG_Byte[5] => Mux68.IN4 
RNG_Byte[6] => Mux51.IN4 
RNG_Byte[6] => Mux59.IN4 
RNG_Byte[6] => Mux67.IN4 
RNG_Byte[7] => Mux50.IN4 
RNG_Byte[7] => Mux58.IN4 
RNG_Byte[7] => Mux66.IN4 
OW_Read_Byte[0] => Equal9.IN15 
OW_Read_Byte[0] => Mux217.IN0 
OW_Read_Byte[0] => Mux225.IN0 
OW_Read_Byte[0] => Mux233.IN0 
OW_Read_Byte[0] => Mux241.IN0 
OW_Read_Byte[1] => Equal9.IN14 
OW_Read_Byte[1] => Mux216.IN0 
OW_Read_Byte[1] => Mux224.IN0 
OW_Read_Byte[1] => Mux232.IN0 
OW_Read_Byte[1] => Mux240.IN0 
OW_Read_Byte[2] => Equal9.IN13 
OW_Read_Byte[2] => Mux215.IN0 
OW_Read_Byte[2] => Mux223.IN0 
OW_Read_Byte[2] => Mux231.IN0 
OW_Read_Byte[2] => Mux239.IN0 
OW_Read_Byte[3] => Equal9.IN12 
OW_Read_Byte[3] => Mux214.IN0 
OW_Read_Byte[3] => Mux222.IN0 
OW_Read_Byte[3] => Mux230.IN0 
OW_Read_Byte[3] => Mux238.IN0 
OW_Read_Byte[4] => Equal9.IN11 
OW_Read_Byte[4] => Mux213.IN0 
OW_Read_Byte[4] => Mux221.IN0 
OW_Read_Byte[4] => Mux229.IN0 
OW_Read_Byte[4] => Mux237.IN0 
OW_Read_Byte[5] => Equal9.IN10 
OW_Read_Byte[5] => Mux212.IN0 
OW_Read_Byte[5] => Mux220.IN0 
OW_Read_Byte[5] => Mux228.IN0 
OW_Read_Byte[5] => Mux236.IN0 
OW_Read_Byte[6] => Equal9.IN9 
OW_Read_Byte[6] => Mux211.IN0 
OW_Read_Byte[6] => Mux219.IN0 
OW_Read_Byte[6] => Mux227.IN0 
OW_Read_Byte[6] => Mux235.IN0 
OW_Read_Byte[7] => Equal9.IN8 
OW_Read_Byte[7] => Mux210.IN0 
OW_Read_Byte[7] => Mux218.IN0 
OW_Read_Byte[7] => Mux226.IN0 
OW_Read_Byte[7] => Mux234.IN0 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => PC_ena.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => rIn.OUTPUTSELECT 
OW_Busy => Selector107.IN3 
OW_Busy => Selector109.IN3 
OW_Busy => Selector110.IN3 
OW_Busy => Selector111.IN3 
OW_Busy => Selector120.IN5 
OW_Busy => Selector120.IN6 
OW_Busy => Selector120.IN7 
OW_Busy => Selector105.IN4 
OW_Busy => Selector105.IN5 
OW_Busy => Selector105.IN6 
OW_No_Device <= OW_No_Device.DB_MAX_OUTPUT_PORT_TYPE 
Enable <= Enable.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4|program_mem:Mem_inst 
address[0] => altsyncram:altsyncram_component.address_a[0] 
address[1] => altsyncram:altsyncram_component.address_a[1] 
address[2] => altsyncram:altsyncram_component.address_a[2] 
address[3] => altsyncram:altsyncram_component.address_a[3] 
address[4] => altsyncram:altsyncram_component.address_a[4] 
address[5] => altsyncram:altsyncram_component.address_a[5] 
address[6] => altsyncram:altsyncram_component.address_a[6] 
address[7] => altsyncram:altsyncram_component.address_a[7] 
clock => altsyncram:altsyncram_component.clock0 
data[0] => altsyncram:altsyncram_component.data_a[0] 
data[1] => altsyncram:altsyncram_component.data_a[1] 
data[2] => altsyncram:altsyncram_component.data_a[2] 
data[3] => altsyncram:altsyncram_component.data_a[3] 
data[4] => altsyncram:altsyncram_component.data_a[4] 
data[5] => altsyncram:altsyncram_component.data_a[5] 
data[6] => altsyncram:altsyncram_component.data_a[6] 
data[7] => altsyncram:altsyncram_component.data_a[7] 
data[8] => altsyncram:altsyncram_component.data_a[8] 
data[9] => altsyncram:altsyncram_component.data_a[9] 
data[10] => altsyncram:altsyncram_component.data_a[10] 
data[11] => altsyncram:altsyncram_component.data_a[11] 
data[12] => altsyncram:altsyncram_component.data_a[12] 
data[13] => altsyncram:altsyncram_component.data_a[13] 
data[14] => altsyncram:altsyncram_component.data_a[14] 
data[15] => altsyncram:altsyncram_component.data_a[15] 
data[16] => altsyncram:altsyncram_component.data_a[16] 
data[17] => altsyncram:altsyncram_component.data_a[17] 
data[18] => altsyncram:altsyncram_component.data_a[18] 
data[19] => altsyncram:altsyncram_component.data_a[19] 
data[20] => altsyncram:altsyncram_component.data_a[20] 
data[21] => altsyncram:altsyncram_component.data_a[21] 
data[22] => altsyncram:altsyncram_component.data_a[22] 
data[23] => altsyncram:altsyncram_component.data_a[23] 
data[24] => altsyncram:altsyncram_component.data_a[24] 
data[25] => altsyncram:altsyncram_component.data_a[25] 
data[26] => altsyncram:altsyncram_component.data_a[26] 
data[27] => altsyncram:altsyncram_component.data_a[27] 
data[28] => altsyncram:altsyncram_component.data_a[28] 
data[29] => altsyncram:altsyncram_component.data_a[29] 
data[30] => altsyncram:altsyncram_component.data_a[30] 
data[31] => altsyncram:altsyncram_component.data_a[31] 
wren => altsyncram:altsyncram_component.wren_a 
q[0] <= altsyncram:altsyncram_component.q_a[0] 
q[1] <= altsyncram:altsyncram_component.q_a[1] 
q[2] <= altsyncram:altsyncram_component.q_a[2] 
q[3] <= altsyncram:altsyncram_component.q_a[3] 
q[4] <= altsyncram:altsyncram_component.q_a[4] 
q[5] <= altsyncram:altsyncram_component.q_a[5] 
q[6] <= altsyncram:altsyncram_component.q_a[6] 
q[7] <= altsyncram:altsyncram_component.q_a[7] 
q[8] <= altsyncram:altsyncram_component.q_a[8] 
q[9] <= altsyncram:altsyncram_component.q_a[9] 
q[10] <= altsyncram:altsyncram_component.q_a[10] 
q[11] <= altsyncram:altsyncram_component.q_a[11] 
q[12] <= altsyncram:altsyncram_component.q_a[12] 
q[13] <= altsyncram:altsyncram_component.q_a[13] 
q[14] <= altsyncram:altsyncram_component.q_a[14] 
q[15] <= altsyncram:altsyncram_component.q_a[15] 
q[16] <= altsyncram:altsyncram_component.q_a[16] 
q[17] <= altsyncram:altsyncram_component.q_a[17] 
q[18] <= altsyncram:altsyncram_component.q_a[18] 
q[19] <= altsyncram:altsyncram_component.q_a[19] 
q[20] <= altsyncram:altsyncram_component.q_a[20] 
q[21] <= altsyncram:altsyncram_component.q_a[21] 
q[22] <= altsyncram:altsyncram_component.q_a[22] 
q[23] <= altsyncram:altsyncram_component.q_a[23] 
q[24] <= altsyncram:altsyncram_component.q_a[24] 
q[25] <= altsyncram:altsyncram_component.q_a[25] 
q[26] <= altsyncram:altsyncram_component.q_a[26] 
q[27] <= altsyncram:altsyncram_component.q_a[27] 
q[28] <= altsyncram:altsyncram_component.q_a[28] 
q[29] <= altsyncram:altsyncram_component.q_a[29] 
q[30] <= altsyncram:altsyncram_component.q_a[30] 
q[31] <= altsyncram:altsyncram_component.q_a[31] 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4|program_mem:Mem_inst|altsyncram:altsyncram_component 
wren_a => altsyncram_vnk1:auto_generated.wren_a 
rden_a => ~NO_FANOUT~ 
wren_b => ~NO_FANOUT~ 
rden_b => ~NO_FANOUT~ 
data_a[0] => altsyncram_vnk1:auto_generated.data_a[0] 
data_a[1] => altsyncram_vnk1:auto_generated.data_a[1] 
data_a[2] => altsyncram_vnk1:auto_generated.data_a[2] 
data_a[3] => altsyncram_vnk1:auto_generated.data_a[3] 
data_a[4] => altsyncram_vnk1:auto_generated.data_a[4] 
data_a[5] => altsyncram_vnk1:auto_generated.data_a[5] 
data_a[6] => altsyncram_vnk1:auto_generated.data_a[6] 
data_a[7] => altsyncram_vnk1:auto_generated.data_a[7] 
data_a[8] => altsyncram_vnk1:auto_generated.data_a[8] 
data_a[9] => altsyncram_vnk1:auto_generated.data_a[9] 
data_a[10] => altsyncram_vnk1:auto_generated.data_a[10] 
data_a[11] => altsyncram_vnk1:auto_generated.data_a[11] 
data_a[12] => altsyncram_vnk1:auto_generated.data_a[12] 
data_a[13] => altsyncram_vnk1:auto_generated.data_a[13] 
data_a[14] => altsyncram_vnk1:auto_generated.data_a[14] 
data_a[15] => altsyncram_vnk1:auto_generated.data_a[15] 
data_a[16] => altsyncram_vnk1:auto_generated.data_a[16] 
data_a[17] => altsyncram_vnk1:auto_generated.data_a[17] 
data_a[18] => altsyncram_vnk1:auto_generated.data_a[18] 
data_a[19] => altsyncram_vnk1:auto_generated.data_a[19] 
data_a[20] => altsyncram_vnk1:auto_generated.data_a[20] 
data_a[21] => altsyncram_vnk1:auto_generated.data_a[21] 
data_a[22] => altsyncram_vnk1:auto_generated.data_a[22] 
data_a[23] => altsyncram_vnk1:auto_generated.data_a[23] 
data_a[24] => altsyncram_vnk1:auto_generated.data_a[24] 
data_a[25] => altsyncram_vnk1:auto_generated.data_a[25] 
data_a[26] => altsyncram_vnk1:auto_generated.data_a[26] 
data_a[27] => altsyncram_vnk1:auto_generated.data_a[27] 
data_a[28] => altsyncram_vnk1:auto_generated.data_a[28] 
data_a[29] => altsyncram_vnk1:auto_generated.data_a[29] 
data_a[30] => altsyncram_vnk1:auto_generated.data_a[30] 
data_a[31] => altsyncram_vnk1:auto_generated.data_a[31] 
data_b[0] => ~NO_FANOUT~ 
address_a[0] => altsyncram_vnk1:auto_generated.address_a[0] 
address_a[1] => altsyncram_vnk1:auto_generated.address_a[1] 
address_a[2] => altsyncram_vnk1:auto_generated.address_a[2] 
address_a[3] => altsyncram_vnk1:auto_generated.address_a[3] 
address_a[4] => altsyncram_vnk1:auto_generated.address_a[4] 
address_a[5] => altsyncram_vnk1:auto_generated.address_a[5] 
address_a[6] => altsyncram_vnk1:auto_generated.address_a[6] 
address_a[7] => altsyncram_vnk1:auto_generated.address_a[7] 
address_b[0] => ~NO_FANOUT~ 
addressstall_a => ~NO_FANOUT~ 
addressstall_b => ~NO_FANOUT~ 
clock0 => altsyncram_vnk1:auto_generated.clock0 
clock1 => ~NO_FANOUT~ 
clocken0 => ~NO_FANOUT~ 
clocken1 => ~NO_FANOUT~ 
clocken2 => ~NO_FANOUT~ 
clocken3 => ~NO_FANOUT~ 
aclr0 => ~NO_FANOUT~ 
aclr1 => ~NO_FANOUT~ 
byteena_a[0] => ~NO_FANOUT~ 
byteena_b[0] => ~NO_FANOUT~ 
q_a[0] <= altsyncram_vnk1:auto_generated.q_a[0] 
q_a[1] <= altsyncram_vnk1:auto_generated.q_a[1] 
q_a[2] <= altsyncram_vnk1:auto_generated.q_a[2] 
q_a[3] <= altsyncram_vnk1:auto_generated.q_a[3] 
q_a[4] <= altsyncram_vnk1:auto_generated.q_a[4] 
q_a[5] <= altsyncram_vnk1:auto_generated.q_a[5] 
q_a[6] <= altsyncram_vnk1:auto_generated.q_a[6] 
q_a[7] <= altsyncram_vnk1:auto_generated.q_a[7] 
q_a[8] <= altsyncram_vnk1:auto_generated.q_a[8] 
q_a[9] <= altsyncram_vnk1:auto_generated.q_a[9] 
q_a[10] <= altsyncram_vnk1:auto_generated.q_a[10] 
q_a[11] <= altsyncram_vnk1:auto_generated.q_a[11] 
q_a[12] <= altsyncram_vnk1:auto_generated.q_a[12] 
q_a[13] <= altsyncram_vnk1:auto_generated.q_a[13] 
q_a[14] <= altsyncram_vnk1:auto_generated.q_a[14] 
q_a[15] <= altsyncram_vnk1:auto_generated.q_a[15] 
q_a[16] <= altsyncram_vnk1:auto_generated.q_a[16] 
q_a[17] <= altsyncram_vnk1:auto_generated.q_a[17] 
q_a[18] <= altsyncram_vnk1:auto_generated.q_a[18] 
q_a[19] <= altsyncram_vnk1:auto_generated.q_a[19] 
q_a[20] <= altsyncram_vnk1:auto_generated.q_a[20] 
q_a[21] <= altsyncram_vnk1:auto_generated.q_a[21] 
q_a[22] <= altsyncram_vnk1:auto_generated.q_a[22] 
q_a[23] <= altsyncram_vnk1:auto_generated.q_a[23] 
q_a[24] <= altsyncram_vnk1:auto_generated.q_a[24] 
q_a[25] <= altsyncram_vnk1:auto_generated.q_a[25] 
q_a[26] <= altsyncram_vnk1:auto_generated.q_a[26] 
q_a[27] <= altsyncram_vnk1:auto_generated.q_a[27] 
q_a[28] <= altsyncram_vnk1:auto_generated.q_a[28] 
q_a[29] <= altsyncram_vnk1:auto_generated.q_a[29] 
q_a[30] <= altsyncram_vnk1:auto_generated.q_a[30] 
q_a[31] <= altsyncram_vnk1:auto_generated.q_a[31] 
q_b[0] <= <GND> 
eccstatus[0] <= <GND> 
eccstatus[1] <= <GND> 
eccstatus[2] <= <GND> 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4|program_mem:Mem_inst|altsyncram:altsyncram_component|altsyncram_vnk1:auto_generated 
address_a[0] => altsyncram_m2b2:altsyncram1.address_a[0] 
address_a[1] => altsyncram_m2b2:altsyncram1.address_a[1] 
address_a[2] => altsyncram_m2b2:altsyncram1.address_a[2] 
address_a[3] => altsyncram_m2b2:altsyncram1.address_a[3] 
address_a[4] => altsyncram_m2b2:altsyncram1.address_a[4] 
address_a[5] => altsyncram_m2b2:altsyncram1.address_a[5] 
address_a[6] => altsyncram_m2b2:altsyncram1.address_a[6] 
address_a[7] => altsyncram_m2b2:altsyncram1.address_a[7] 
clock0 => altsyncram_m2b2:altsyncram1.clock0 
data_a[0] => altsyncram_m2b2:altsyncram1.data_a[0] 
data_a[1] => altsyncram_m2b2:altsyncram1.data_a[1] 
data_a[2] => altsyncram_m2b2:altsyncram1.data_a[2] 
data_a[3] => altsyncram_m2b2:altsyncram1.data_a[3] 
data_a[4] => altsyncram_m2b2:altsyncram1.data_a[4] 
data_a[5] => altsyncram_m2b2:altsyncram1.data_a[5] 
data_a[6] => altsyncram_m2b2:altsyncram1.data_a[6] 
data_a[7] => altsyncram_m2b2:altsyncram1.data_a[7] 
data_a[8] => altsyncram_m2b2:altsyncram1.data_a[8] 
data_a[9] => altsyncram_m2b2:altsyncram1.data_a[9] 
data_a[10] => altsyncram_m2b2:altsyncram1.data_a[10] 
data_a[11] => altsyncram_m2b2:altsyncram1.data_a[11] 
data_a[12] => altsyncram_m2b2:altsyncram1.data_a[12] 
data_a[13] => altsyncram_m2b2:altsyncram1.data_a[13] 
data_a[14] => altsyncram_m2b2:altsyncram1.data_a[14] 
data_a[15] => altsyncram_m2b2:altsyncram1.data_a[15] 
data_a[16] => altsyncram_m2b2:altsyncram1.data_a[16] 
data_a[17] => altsyncram_m2b2:altsyncram1.data_a[17] 
data_a[18] => altsyncram_m2b2:altsyncram1.data_a[18] 
data_a[19] => altsyncram_m2b2:altsyncram1.data_a[19] 
data_a[20] => altsyncram_m2b2:altsyncram1.data_a[20] 
data_a[21] => altsyncram_m2b2:altsyncram1.data_a[21] 
data_a[22] => altsyncram_m2b2:altsyncram1.data_a[22] 
data_a[23] => altsyncram_m2b2:altsyncram1.data_a[23] 
data_a[24] => altsyncram_m2b2:altsyncram1.data_a[24] 
data_a[25] => altsyncram_m2b2:altsyncram1.data_a[25] 
data_a[26] => altsyncram_m2b2:altsyncram1.data_a[26] 
data_a[27] => altsyncram_m2b2:altsyncram1.data_a[27] 
data_a[28] => altsyncram_m2b2:altsyncram1.data_a[28] 
data_a[29] => altsyncram_m2b2:altsyncram1.data_a[29] 
data_a[30] => altsyncram_m2b2:altsyncram1.data_a[30] 
data_a[31] => altsyncram_m2b2:altsyncram1.data_a[31] 
q_a[0] <= altsyncram_m2b2:altsyncram1.q_a[0] 
q_a[1] <= altsyncram_m2b2:altsyncram1.q_a[1] 
q_a[2] <= altsyncram_m2b2:altsyncram1.q_a[2] 
q_a[3] <= altsyncram_m2b2:altsyncram1.q_a[3] 
q_a[4] <= altsyncram_m2b2:altsyncram1.q_a[4] 
q_a[5] <= altsyncram_m2b2:altsyncram1.q_a[5] 
q_a[6] <= altsyncram_m2b2:altsyncram1.q_a[6] 
q_a[7] <= altsyncram_m2b2:altsyncram1.q_a[7] 
q_a[8] <= altsyncram_m2b2:altsyncram1.q_a[8] 
q_a[9] <= altsyncram_m2b2:altsyncram1.q_a[9] 
q_a[10] <= altsyncram_m2b2:altsyncram1.q_a[10] 
q_a[11] <= altsyncram_m2b2:altsyncram1.q_a[11] 
q_a[12] <= altsyncram_m2b2:altsyncram1.q_a[12] 
q_a[13] <= altsyncram_m2b2:altsyncram1.q_a[13] 
q_a[14] <= altsyncram_m2b2:altsyncram1.q_a[14] 
q_a[15] <= altsyncram_m2b2:altsyncram1.q_a[15] 
q_a[16] <= altsyncram_m2b2:altsyncram1.q_a[16] 
q_a[17] <= altsyncram_m2b2:altsyncram1.q_a[17] 
q_a[18] <= altsyncram_m2b2:altsyncram1.q_a[18] 
q_a[19] <= altsyncram_m2b2:altsyncram1.q_a[19] 
q_a[20] <= altsyncram_m2b2:altsyncram1.q_a[20] 
q_a[21] <= altsyncram_m2b2:altsyncram1.q_a[21] 
q_a[22] <= altsyncram_m2b2:altsyncram1.q_a[22] 
q_a[23] <= altsyncram_m2b2:altsyncram1.q_a[23] 
q_a[24] <= altsyncram_m2b2:altsyncram1.q_a[24] 
q_a[25] <= altsyncram_m2b2:altsyncram1.q_a[25] 
q_a[26] <= altsyncram_m2b2:altsyncram1.q_a[26] 
q_a[27] <= altsyncram_m2b2:altsyncram1.q_a[27] 
q_a[28] <= altsyncram_m2b2:altsyncram1.q_a[28] 
q_a[29] <= altsyncram_m2b2:altsyncram1.q_a[29] 
q_a[30] <= altsyncram_m2b2:altsyncram1.q_a[30] 
q_a[31] <= altsyncram_m2b2:altsyncram1.q_a[31] 
wren_a => altsyncram_m2b2:altsyncram1.wren_a 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4|program_mem:Mem_inst|altsyncram:altsyncram_component|altsyncram_vnk1:auto_generated|altsyncram_m2b2:altsyncram1 
address_a[0] => ram_block3a0.PORTAADDR 
address_a[0] => ram_block3a1.PORTAADDR 
address_a[0] => ram_block3a2.PORTAADDR 
address_a[0] => ram_block3a3.PORTAADDR 
address_a[0] => ram_block3a4.PORTAADDR 
address_a[0] => ram_block3a5.PORTAADDR 
address_a[0] => ram_block3a6.PORTAADDR 
address_a[0] => ram_block3a7.PORTAADDR 
address_a[0] => ram_block3a8.PORTAADDR 
address_a[0] => ram_block3a9.PORTAADDR 
address_a[0] => ram_block3a10.PORTAADDR 
address_a[0] => ram_block3a11.PORTAADDR 
address_a[0] => ram_block3a12.PORTAADDR 
address_a[0] => ram_block3a13.PORTAADDR 
address_a[0] => ram_block3a14.PORTAADDR 
address_a[0] => ram_block3a15.PORTAADDR 
address_a[0] => ram_block3a16.PORTAADDR 
address_a[0] => ram_block3a17.PORTAADDR 
address_a[0] => ram_block3a18.PORTAADDR 
address_a[0] => ram_block3a19.PORTAADDR 
address_a[0] => ram_block3a20.PORTAADDR 
address_a[0] => ram_block3a21.PORTAADDR 
address_a[0] => ram_block3a22.PORTAADDR 
address_a[0] => ram_block3a23.PORTAADDR 
address_a[0] => ram_block3a24.PORTAADDR 
address_a[0] => ram_block3a25.PORTAADDR 
address_a[0] => ram_block3a26.PORTAADDR 
address_a[0] => ram_block3a27.PORTAADDR 
address_a[0] => ram_block3a28.PORTAADDR 
address_a[0] => ram_block3a29.PORTAADDR 
address_a[0] => ram_block3a30.PORTAADDR 
address_a[0] => ram_block3a31.PORTAADDR 
address_a[1] => ram_block3a0.PORTAADDR1 
address_a[1] => ram_block3a1.PORTAADDR1 
address_a[1] => ram_block3a2.PORTAADDR1 
address_a[1] => ram_block3a3.PORTAADDR1 
address_a[1] => ram_block3a4.PORTAADDR1 
address_a[1] => ram_block3a5.PORTAADDR1 
address_a[1] => ram_block3a6.PORTAADDR1 
address_a[1] => ram_block3a7.PORTAADDR1 
address_a[1] => ram_block3a8.PORTAADDR1 
address_a[1] => ram_block3a9.PORTAADDR1 
address_a[1] => ram_block3a10.PORTAADDR1 
address_a[1] => ram_block3a11.PORTAADDR1 
address_a[1] => ram_block3a12.PORTAADDR1 
address_a[1] => ram_block3a13.PORTAADDR1 
address_a[1] => ram_block3a14.PORTAADDR1 
address_a[1] => ram_block3a15.PORTAADDR1 
address_a[1] => ram_block3a16.PORTAADDR1 
address_a[1] => ram_block3a17.PORTAADDR1 
address_a[1] => ram_block3a18.PORTAADDR1 
address_a[1] => ram_block3a19.PORTAADDR1 
address_a[1] => ram_block3a20.PORTAADDR1 
address_a[1] => ram_block3a21.PORTAADDR1 
address_a[1] => ram_block3a22.PORTAADDR1 
address_a[1] => ram_block3a23.PORTAADDR1 
address_a[1] => ram_block3a24.PORTAADDR1 
address_a[1] => ram_block3a25.PORTAADDR1 
address_a[1] => ram_block3a26.PORTAADDR1 
address_a[1] => ram_block3a27.PORTAADDR1 
address_a[1] => ram_block3a28.PORTAADDR1 
address_a[1] => ram_block3a29.PORTAADDR1 
address_a[1] => ram_block3a30.PORTAADDR1 
address_a[1] => ram_block3a31.PORTAADDR1 
address_a[2] => ram_block3a0.PORTAADDR2 
address_a[2] => ram_block3a1.PORTAADDR2 
address_a[2] => ram_block3a2.PORTAADDR2 
address_a[2] => ram_block3a3.PORTAADDR2 
address_a[2] => ram_block3a4.PORTAADDR2 
address_a[2] => ram_block3a5.PORTAADDR2 
address_a[2] => ram_block3a6.PORTAADDR2 
address_a[2] => ram_block3a7.PORTAADDR2 
address_a[2] => ram_block3a8.PORTAADDR2 
address_a[2] => ram_block3a9.PORTAADDR2 
address_a[2] => ram_block3a10.PORTAADDR2 
address_a[2] => ram_block3a11.PORTAADDR2 
address_a[2] => ram_block3a12.PORTAADDR2 
address_a[2] => ram_block3a13.PORTAADDR2 
address_a[2] => ram_block3a14.PORTAADDR2 
address_a[2] => ram_block3a15.PORTAADDR2 
address_a[2] => ram_block3a16.PORTAADDR2 
address_a[2] => ram_block3a17.PORTAADDR2 
address_a[2] => ram_block3a18.PORTAADDR2 
address_a[2] => ram_block3a19.PORTAADDR2 
address_a[2] => ram_block3a20.PORTAADDR2 
address_a[2] => ram_block3a21.PORTAADDR2 
address_a[2] => ram_block3a22.PORTAADDR2 
address_a[2] => ram_block3a23.PORTAADDR2 
address_a[2] => ram_block3a24.PORTAADDR2 
address_a[2] => ram_block3a25.PORTAADDR2 
address_a[2] => ram_block3a26.PORTAADDR2 
address_a[2] => ram_block3a27.PORTAADDR2 
address_a[2] => ram_block3a28.PORTAADDR2 
address_a[2] => ram_block3a29.PORTAADDR2 
address_a[2] => ram_block3a30.PORTAADDR2 
address_a[2] => ram_block3a31.PORTAADDR2 
address_a[3] => ram_block3a0.PORTAADDR3 
address_a[3] => ram_block3a1.PORTAADDR3 
address_a[3] => ram_block3a2.PORTAADDR3 
address_a[3] => ram_block3a3.PORTAADDR3 
address_a[3] => ram_block3a4.PORTAADDR3 
address_a[3] => ram_block3a5.PORTAADDR3 
address_a[3] => ram_block3a6.PORTAADDR3 
address_a[3] => ram_block3a7.PORTAADDR3 
address_a[3] => ram_block3a8.PORTAADDR3 
address_a[3] => ram_block3a9.PORTAADDR3 
address_a[3] => ram_block3a10.PORTAADDR3 
address_a[3] => ram_block3a11.PORTAADDR3 
address_a[3] => ram_block3a12.PORTAADDR3 
address_a[3] => ram_block3a13.PORTAADDR3 
address_a[3] => ram_block3a14.PORTAADDR3 
address_a[3] => ram_block3a15.PORTAADDR3 
address_a[3] => ram_block3a16.PORTAADDR3 
address_a[3] => ram_block3a17.PORTAADDR3 
address_a[3] => ram_block3a18.PORTAADDR3 
address_a[3] => ram_block3a19.PORTAADDR3 
address_a[3] => ram_block3a20.PORTAADDR3 
address_a[3] => ram_block3a21.PORTAADDR3 
address_a[3] => ram_block3a22.PORTAADDR3 
address_a[3] => ram_block3a23.PORTAADDR3 
address_a[3] => ram_block3a24.PORTAADDR3 
address_a[3] => ram_block3a25.PORTAADDR3 
address_a[3] => ram_block3a26.PORTAADDR3 
address_a[3] => ram_block3a27.PORTAADDR3 
address_a[3] => ram_block3a28.PORTAADDR3 
address_a[3] => ram_block3a29.PORTAADDR3 
address_a[3] => ram_block3a30.PORTAADDR3 
address_a[3] => ram_block3a31.PORTAADDR3 
address_a[4] => ram_block3a0.PORTAADDR4 
address_a[4] => ram_block3a1.PORTAADDR4 
address_a[4] => ram_block3a2.PORTAADDR4 
address_a[4] => ram_block3a3.PORTAADDR4 
address_a[4] => ram_block3a4.PORTAADDR4 
address_a[4] => ram_block3a5.PORTAADDR4 
address_a[4] => ram_block3a6.PORTAADDR4 
address_a[4] => ram_block3a7.PORTAADDR4 
address_a[4] => ram_block3a8.PORTAADDR4 
address_a[4] => ram_block3a9.PORTAADDR4 
address_a[4] => ram_block3a10.PORTAADDR4 
address_a[4] => ram_block3a11.PORTAADDR4 
address_a[4] => ram_block3a12.PORTAADDR4 
address_a[4] => ram_block3a13.PORTAADDR4 
address_a[4] => ram_block3a14.PORTAADDR4 
address_a[4] => ram_block3a15.PORTAADDR4 
address_a[4] => ram_block3a16.PORTAADDR4 
address_a[4] => ram_block3a17.PORTAADDR4 
address_a[4] => ram_block3a18.PORTAADDR4 
address_a[4] => ram_block3a19.PORTAADDR4 
address_a[4] => ram_block3a20.PORTAADDR4 
address_a[4] => ram_block3a21.PORTAADDR4 
address_a[4] => ram_block3a22.PORTAADDR4 
address_a[4] => ram_block3a23.PORTAADDR4 
address_a[4] => ram_block3a24.PORTAADDR4 
address_a[4] => ram_block3a25.PORTAADDR4 
address_a[4] => ram_block3a26.PORTAADDR4 
address_a[4] => ram_block3a27.PORTAADDR4 
address_a[4] => ram_block3a28.PORTAADDR4 
address_a[4] => ram_block3a29.PORTAADDR4 
address_a[4] => ram_block3a30.PORTAADDR4 
address_a[4] => ram_block3a31.PORTAADDR4 
address_a[5] => ram_block3a0.PORTAADDR5 
address_a[5] => ram_block3a1.PORTAADDR5 
address_a[5] => ram_block3a2.PORTAADDR5 
address_a[5] => ram_block3a3.PORTAADDR5 
address_a[5] => ram_block3a4.PORTAADDR5 
address_a[5] => ram_block3a5.PORTAADDR5 
address_a[5] => ram_block3a6.PORTAADDR5 
address_a[5] => ram_block3a7.PORTAADDR5 
address_a[5] => ram_block3a8.PORTAADDR5 
address_a[5] => ram_block3a9.PORTAADDR5 
address_a[5] => ram_block3a10.PORTAADDR5 
address_a[5] => ram_block3a11.PORTAADDR5 
address_a[5] => ram_block3a12.PORTAADDR5 
address_a[5] => ram_block3a13.PORTAADDR5 
address_a[5] => ram_block3a14.PORTAADDR5 
address_a[5] => ram_block3a15.PORTAADDR5 
address_a[5] => ram_block3a16.PORTAADDR5 
address_a[5] => ram_block3a17.PORTAADDR5 
address_a[5] => ram_block3a18.PORTAADDR5 
address_a[5] => ram_block3a19.PORTAADDR5 
address_a[5] => ram_block3a20.PORTAADDR5 
address_a[5] => ram_block3a21.PORTAADDR5 
address_a[5] => ram_block3a22.PORTAADDR5 
address_a[5] => ram_block3a23.PORTAADDR5 
address_a[5] => ram_block3a24.PORTAADDR5 
address_a[5] => ram_block3a25.PORTAADDR5 
address_a[5] => ram_block3a26.PORTAADDR5 
address_a[5] => ram_block3a27.PORTAADDR5 
address_a[5] => ram_block3a28.PORTAADDR5 
address_a[5] => ram_block3a29.PORTAADDR5 
address_a[5] => ram_block3a30.PORTAADDR5 
address_a[5] => ram_block3a31.PORTAADDR5 
address_a[6] => ram_block3a0.PORTAADDR6 
address_a[6] => ram_block3a1.PORTAADDR6 
address_a[6] => ram_block3a2.PORTAADDR6 
address_a[6] => ram_block3a3.PORTAADDR6 
address_a[6] => ram_block3a4.PORTAADDR6 
address_a[6] => ram_block3a5.PORTAADDR6 
address_a[6] => ram_block3a6.PORTAADDR6 
address_a[6] => ram_block3a7.PORTAADDR6 
address_a[6] => ram_block3a8.PORTAADDR6 
address_a[6] => ram_block3a9.PORTAADDR6 
address_a[6] => ram_block3a10.PORTAADDR6 
address_a[6] => ram_block3a11.PORTAADDR6 
address_a[6] => ram_block3a12.PORTAADDR6 
address_a[6] => ram_block3a13.PORTAADDR6 
address_a[6] => ram_block3a14.PORTAADDR6 
address_a[6] => ram_block3a15.PORTAADDR6 
address_a[6] => ram_block3a16.PORTAADDR6 
address_a[6] => ram_block3a17.PORTAADDR6 
address_a[6] => ram_block3a18.PORTAADDR6 
address_a[6] => ram_block3a19.PORTAADDR6 
address_a[6] => ram_block3a20.PORTAADDR6 
address_a[6] => ram_block3a21.PORTAADDR6 
address_a[6] => ram_block3a22.PORTAADDR6 
address_a[6] => ram_block3a23.PORTAADDR6 
address_a[6] => ram_block3a24.PORTAADDR6 
address_a[6] => ram_block3a25.PORTAADDR6 
address_a[6] => ram_block3a26.PORTAADDR6 
address_a[6] => ram_block3a27.PORTAADDR6 
address_a[6] => ram_block3a28.PORTAADDR6 
address_a[6] => ram_block3a29.PORTAADDR6 
address_a[6] => ram_block3a30.PORTAADDR6 
address_a[6] => ram_block3a31.PORTAADDR6 
address_a[7] => ram_block3a0.PORTAADDR7 
address_a[7] => ram_block3a1.PORTAADDR7 
address_a[7] => ram_block3a2.PORTAADDR7 
address_a[7] => ram_block3a3.PORTAADDR7 
address_a[7] => ram_block3a4.PORTAADDR7 
address_a[7] => ram_block3a5.PORTAADDR7 
address_a[7] => ram_block3a6.PORTAADDR7 
address_a[7] => ram_block3a7.PORTAADDR7 
address_a[7] => ram_block3a8.PORTAADDR7 
address_a[7] => ram_block3a9.PORTAADDR7 
address_a[7] => ram_block3a10.PORTAADDR7 
address_a[7] => ram_block3a11.PORTAADDR7 
address_a[7] => ram_block3a12.PORTAADDR7 
address_a[7] => ram_block3a13.PORTAADDR7 
address_a[7] => ram_block3a14.PORTAADDR7 
address_a[7] => ram_block3a15.PORTAADDR7 
address_a[7] => ram_block3a16.PORTAADDR7 
address_a[7] => ram_block3a17.PORTAADDR7 
address_a[7] => ram_block3a18.PORTAADDR7 
address_a[7] => ram_block3a19.PORTAADDR7 
address_a[7] => ram_block3a20.PORTAADDR7 
address_a[7] => ram_block3a21.PORTAADDR7 
address_a[7] => ram_block3a22.PORTAADDR7 
address_a[7] => ram_block3a23.PORTAADDR7 
address_a[7] => ram_block3a24.PORTAADDR7 
address_a[7] => ram_block3a25.PORTAADDR7 
address_a[7] => ram_block3a26.PORTAADDR7 
address_a[7] => ram_block3a27.PORTAADDR7 
address_a[7] => ram_block3a28.PORTAADDR7 
address_a[7] => ram_block3a29.PORTAADDR7 
address_a[7] => ram_block3a30.PORTAADDR7 
address_a[7] => ram_block3a31.PORTAADDR7 
address_b[0] => ram_block3a0.PORTBADDR 
address_b[0] => ram_block3a1.PORTBADDR 
address_b[0] => ram_block3a2.PORTBADDR 
address_b[0] => ram_block3a3.PORTBADDR 
address_b[0] => ram_block3a4.PORTBADDR 
address_b[0] => ram_block3a5.PORTBADDR 
address_b[0] => ram_block3a6.PORTBADDR 
address_b[0] => ram_block3a7.PORTBADDR 
address_b[0] => ram_block3a8.PORTBADDR 
address_b[0] => ram_block3a9.PORTBADDR 
address_b[0] => ram_block3a10.PORTBADDR 
address_b[0] => ram_block3a11.PORTBADDR 
address_b[0] => ram_block3a12.PORTBADDR 
address_b[0] => ram_block3a13.PORTBADDR 
address_b[0] => ram_block3a14.PORTBADDR 
address_b[0] => ram_block3a15.PORTBADDR 
address_b[0] => ram_block3a16.PORTBADDR 
address_b[0] => ram_block3a17.PORTBADDR 
address_b[0] => ram_block3a18.PORTBADDR 
address_b[0] => ram_block3a19.PORTBADDR 
address_b[0] => ram_block3a20.PORTBADDR 
address_b[0] => ram_block3a21.PORTBADDR 
address_b[0] => ram_block3a22.PORTBADDR 
address_b[0] => ram_block3a23.PORTBADDR 
address_b[0] => ram_block3a24.PORTBADDR 
address_b[0] => ram_block3a25.PORTBADDR 
address_b[0] => ram_block3a26.PORTBADDR 
address_b[0] => ram_block3a27.PORTBADDR 
address_b[0] => ram_block3a28.PORTBADDR 
address_b[0] => ram_block3a29.PORTBADDR 
address_b[0] => ram_block3a30.PORTBADDR 
address_b[0] => ram_block3a31.PORTBADDR 
address_b[1] => ram_block3a0.PORTBADDR1 
address_b[1] => ram_block3a1.PORTBADDR1 
address_b[1] => ram_block3a2.PORTBADDR1 
address_b[1] => ram_block3a3.PORTBADDR1 
address_b[1] => ram_block3a4.PORTBADDR1 
address_b[1] => ram_block3a5.PORTBADDR1 
address_b[1] => ram_block3a6.PORTBADDR1 
address_b[1] => ram_block3a7.PORTBADDR1 
address_b[1] => ram_block3a8.PORTBADDR1 
address_b[1] => ram_block3a9.PORTBADDR1 
address_b[1] => ram_block3a10.PORTBADDR1 
address_b[1] => ram_block3a11.PORTBADDR1 
address_b[1] => ram_block3a12.PORTBADDR1 
address_b[1] => ram_block3a13.PORTBADDR1 
address_b[1] => ram_block3a14.PORTBADDR1 
address_b[1] => ram_block3a15.PORTBADDR1 
address_b[1] => ram_block3a16.PORTBADDR1 
address_b[1] => ram_block3a17.PORTBADDR1 
address_b[1] => ram_block3a18.PORTBADDR1 
address_b[1] => ram_block3a19.PORTBADDR1 
address_b[1] => ram_block3a20.PORTBADDR1 
address_b[1] => ram_block3a21.PORTBADDR1 
address_b[1] => ram_block3a22.PORTBADDR1 
address_b[1] => ram_block3a23.PORTBADDR1 
address_b[1] => ram_block3a24.PORTBADDR1 
address_b[1] => ram_block3a25.PORTBADDR1 
address_b[1] => ram_block3a26.PORTBADDR1 
address_b[1] => ram_block3a27.PORTBADDR1 
address_b[1] => ram_block3a28.PORTBADDR1 
address_b[1] => ram_block3a29.PORTBADDR1 
address_b[1] => ram_block3a30.PORTBADDR1 
address_b[1] => ram_block3a31.PORTBADDR1 
address_b[2] => ram_block3a0.PORTBADDR2 
address_b[2] => ram_block3a1.PORTBADDR2 
address_b[2] => ram_block3a2.PORTBADDR2 
address_b[2] => ram_block3a3.PORTBADDR2 
address_b[2] => ram_block3a4.PORTBADDR2 
address_b[2] => ram_block3a5.PORTBADDR2 
address_b[2] => ram_block3a6.PORTBADDR2 
address_b[2] => ram_block3a7.PORTBADDR2 
address_b[2] => ram_block3a8.PORTBADDR2 
address_b[2] => ram_block3a9.PORTBADDR2 
address_b[2] => ram_block3a10.PORTBADDR2 
address_b[2] => ram_block3a11.PORTBADDR2 
address_b[2] => ram_block3a12.PORTBADDR2 
address_b[2] => ram_block3a13.PORTBADDR2 
address_b[2] => ram_block3a14.PORTBADDR2 
address_b[2] => ram_block3a15.PORTBADDR2 
address_b[2] => ram_block3a16.PORTBADDR2 
address_b[2] => ram_block3a17.PORTBADDR2 
address_b[2] => ram_block3a18.PORTBADDR2 
address_b[2] => ram_block3a19.PORTBADDR2 
address_b[2] => ram_block3a20.PORTBADDR2 
address_b[2] => ram_block3a21.PORTBADDR2 
address_b[2] => ram_block3a22.PORTBADDR2 
address_b[2] => ram_block3a23.PORTBADDR2 
address_b[2] => ram_block3a24.PORTBADDR2 
address_b[2] => ram_block3a25.PORTBADDR2 
address_b[2] => ram_block3a26.PORTBADDR2 
address_b[2] => ram_block3a27.PORTBADDR2 
address_b[2] => ram_block3a28.PORTBADDR2 
address_b[2] => ram_block3a29.PORTBADDR2 
address_b[2] => ram_block3a30.PORTBADDR2 
address_b[2] => ram_block3a31.PORTBADDR2 
address_b[3] => ram_block3a0.PORTBADDR3 
address_b[3] => ram_block3a1.PORTBADDR3 
address_b[3] => ram_block3a2.PORTBADDR3 
address_b[3] => ram_block3a3.PORTBADDR3 
address_b[3] => ram_block3a4.PORTBADDR3 
address_b[3] => ram_block3a5.PORTBADDR3 
address_b[3] => ram_block3a6.PORTBADDR3 
address_b[3] => ram_block3a7.PORTBADDR3 
address_b[3] => ram_block3a8.PORTBADDR3 
address_b[3] => ram_block3a9.PORTBADDR3 
address_b[3] => ram_block3a10.PORTBADDR3 
address_b[3] => ram_block3a11.PORTBADDR3 
address_b[3] => ram_block3a12.PORTBADDR3 
address_b[3] => ram_block3a13.PORTBADDR3 
address_b[3] => ram_block3a14.PORTBADDR3 
address_b[3] => ram_block3a15.PORTBADDR3 
address_b[3] => ram_block3a16.PORTBADDR3 
address_b[3] => ram_block3a17.PORTBADDR3 
address_b[3] => ram_block3a18.PORTBADDR3 
address_b[3] => ram_block3a19.PORTBADDR3 
address_b[3] => ram_block3a20.PORTBADDR3 
address_b[3] => ram_block3a21.PORTBADDR3 
address_b[3] => ram_block3a22.PORTBADDR3 
address_b[3] => ram_block3a23.PORTBADDR3 
address_b[3] => ram_block3a24.PORTBADDR3 
address_b[3] => ram_block3a25.PORTBADDR3 
address_b[3] => ram_block3a26.PORTBADDR3 
address_b[3] => ram_block3a27.PORTBADDR3 
address_b[3] => ram_block3a28.PORTBADDR3 
address_b[3] => ram_block3a29.PORTBADDR3 
address_b[3] => ram_block3a30.PORTBADDR3 
address_b[3] => ram_block3a31.PORTBADDR3 
address_b[4] => ram_block3a0.PORTBADDR4 
address_b[4] => ram_block3a1.PORTBADDR4 
address_b[4] => ram_block3a2.PORTBADDR4 
address_b[4] => ram_block3a3.PORTBADDR4 
address_b[4] => ram_block3a4.PORTBADDR4 
address_b[4] => ram_block3a5.PORTBADDR4 
address_b[4] => ram_block3a6.PORTBADDR4 
address_b[4] => ram_block3a7.PORTBADDR4 
address_b[4] => ram_block3a8.PORTBADDR4 
address_b[4] => ram_block3a9.PORTBADDR4 
address_b[4] => ram_block3a10.PORTBADDR4 
address_b[4] => ram_block3a11.PORTBADDR4 
address_b[4] => ram_block3a12.PORTBADDR4 
address_b[4] => ram_block3a13.PORTBADDR4 
address_b[4] => ram_block3a14.PORTBADDR4 
address_b[4] => ram_block3a15.PORTBADDR4 
address_b[4] => ram_block3a16.PORTBADDR4 
address_b[4] => ram_block3a17.PORTBADDR4 
address_b[4] => ram_block3a18.PORTBADDR4 
address_b[4] => ram_block3a19.PORTBADDR4 
address_b[4] => ram_block3a20.PORTBADDR4 
address_b[4] => ram_block3a21.PORTBADDR4 
address_b[4] => ram_block3a22.PORTBADDR4 
address_b[4] => ram_block3a23.PORTBADDR4 
address_b[4] => ram_block3a24.PORTBADDR4 
address_b[4] => ram_block3a25.PORTBADDR4 
address_b[4] => ram_block3a26.PORTBADDR4 
address_b[4] => ram_block3a27.PORTBADDR4 
address_b[4] => ram_block3a28.PORTBADDR4 
address_b[4] => ram_block3a29.PORTBADDR4 
address_b[4] => ram_block3a30.PORTBADDR4 
address_b[4] => ram_block3a31.PORTBADDR4 
address_b[5] => ram_block3a0.PORTBADDR5 
address_b[5] => ram_block3a1.PORTBADDR5 
address_b[5] => ram_block3a2.PORTBADDR5 
address_b[5] => ram_block3a3.PORTBADDR5 
address_b[5] => ram_block3a4.PORTBADDR5 
address_b[5] => ram_block3a5.PORTBADDR5 
address_b[5] => ram_block3a6.PORTBADDR5 
address_b[5] => ram_block3a7.PORTBADDR5 
address_b[5] => ram_block3a8.PORTBADDR5 
address_b[5] => ram_block3a9.PORTBADDR5 
address_b[5] => ram_block3a10.PORTBADDR5 
address_b[5] => ram_block3a11.PORTBADDR5 
address_b[5] => ram_block3a12.PORTBADDR5 
address_b[5] => ram_block3a13.PORTBADDR5 
address_b[5] => ram_block3a14.PORTBADDR5 
address_b[5] => ram_block3a15.PORTBADDR5 
address_b[5] => ram_block3a16.PORTBADDR5 
address_b[5] => ram_block3a17.PORTBADDR5 
address_b[5] => ram_block3a18.PORTBADDR5 
address_b[5] => ram_block3a19.PORTBADDR5 
address_b[5] => ram_block3a20.PORTBADDR5 
address_b[5] => ram_block3a21.PORTBADDR5 
address_b[5] => ram_block3a22.PORTBADDR5 
address_b[5] => ram_block3a23.PORTBADDR5 
address_b[5] => ram_block3a24.PORTBADDR5 
address_b[5] => ram_block3a25.PORTBADDR5 
address_b[5] => ram_block3a26.PORTBADDR5 
address_b[5] => ram_block3a27.PORTBADDR5 
address_b[5] => ram_block3a28.PORTBADDR5 
address_b[5] => ram_block3a29.PORTBADDR5 
address_b[5] => ram_block3a30.PORTBADDR5 
address_b[5] => ram_block3a31.PORTBADDR5 
address_b[6] => ram_block3a0.PORTBADDR6 
address_b[6] => ram_block3a1.PORTBADDR6 
address_b[6] => ram_block3a2.PORTBADDR6 
address_b[6] => ram_block3a3.PORTBADDR6 
address_b[6] => ram_block3a4.PORTBADDR6 
address_b[6] => ram_block3a5.PORTBADDR6 
address_b[6] => ram_block3a6.PORTBADDR6 
address_b[6] => ram_block3a7.PORTBADDR6 
address_b[6] => ram_block3a8.PORTBADDR6 
address_b[6] => ram_block3a9.PORTBADDR6 
address_b[6] => ram_block3a10.PORTBADDR6 
address_b[6] => ram_block3a11.PORTBADDR6 
address_b[6] => ram_block3a12.PORTBADDR6 
address_b[6] => ram_block3a13.PORTBADDR6 
address_b[6] => ram_block3a14.PORTBADDR6 
address_b[6] => ram_block3a15.PORTBADDR6 
address_b[6] => ram_block3a16.PORTBADDR6 
address_b[6] => ram_block3a17.PORTBADDR6 
address_b[6] => ram_block3a18.PORTBADDR6 
address_b[6] => ram_block3a19.PORTBADDR6 
address_b[6] => ram_block3a20.PORTBADDR6 
address_b[6] => ram_block3a21.PORTBADDR6 
address_b[6] => ram_block3a22.PORTBADDR6 
address_b[6] => ram_block3a23.PORTBADDR6 
address_b[6] => ram_block3a24.PORTBADDR6 
address_b[6] => ram_block3a25.PORTBADDR6 
address_b[6] => ram_block3a26.PORTBADDR6 
address_b[6] => ram_block3a27.PORTBADDR6 
address_b[6] => ram_block3a28.PORTBADDR6 
address_b[6] => ram_block3a29.PORTBADDR6 
address_b[6] => ram_block3a30.PORTBADDR6 
address_b[6] => ram_block3a31.PORTBADDR6 
address_b[7] => ram_block3a0.PORTBADDR7 
address_b[7] => ram_block3a1.PORTBADDR7 
address_b[7] => ram_block3a2.PORTBADDR7 
address_b[7] => ram_block3a3.PORTBADDR7 
address_b[7] => ram_block3a4.PORTBADDR7 
address_b[7] => ram_block3a5.PORTBADDR7 
address_b[7] => ram_block3a6.PORTBADDR7 
address_b[7] => ram_block3a7.PORTBADDR7 
address_b[7] => ram_block3a8.PORTBADDR7 
address_b[7] => ram_block3a9.PORTBADDR7 
address_b[7] => ram_block3a10.PORTBADDR7 
address_b[7] => ram_block3a11.PORTBADDR7 
address_b[7] => ram_block3a12.PORTBADDR7 
address_b[7] => ram_block3a13.PORTBADDR7 
address_b[7] => ram_block3a14.PORTBADDR7 
address_b[7] => ram_block3a15.PORTBADDR7 
address_b[7] => ram_block3a16.PORTBADDR7 
address_b[7] => ram_block3a17.PORTBADDR7 
address_b[7] => ram_block3a18.PORTBADDR7 
address_b[7] => ram_block3a19.PORTBADDR7 
address_b[7] => ram_block3a20.PORTBADDR7 
address_b[7] => ram_block3a21.PORTBADDR7 
address_b[7] => ram_block3a22.PORTBADDR7 
address_b[7] => ram_block3a23.PORTBADDR7 
address_b[7] => ram_block3a24.PORTBADDR7 
address_b[7] => ram_block3a25.PORTBADDR7 
address_b[7] => ram_block3a26.PORTBADDR7 
address_b[7] => ram_block3a27.PORTBADDR7 
address_b[7] => ram_block3a28.PORTBADDR7 
address_b[7] => ram_block3a29.PORTBADDR7 
address_b[7] => ram_block3a30.PORTBADDR7 
address_b[7] => ram_block3a31.PORTBADDR7 
clock0 => ram_block3a0.CLK0 
clock0 => ram_block3a1.CLK0 
clock0 => ram_block3a2.CLK0 
clock0 => ram_block3a3.CLK0 
clock0 => ram_block3a4.CLK0 
clock0 => ram_block3a5.CLK0 
clock0 => ram_block3a6.CLK0 
clock0 => ram_block3a7.CLK0 
clock0 => ram_block3a8.CLK0 
clock0 => ram_block3a9.CLK0 
clock0 => ram_block3a10.CLK0 
clock0 => ram_block3a11.CLK0 
clock0 => ram_block3a12.CLK0 
clock0 => ram_block3a13.CLK0 
clock0 => ram_block3a14.CLK0 
clock0 => ram_block3a15.CLK0 
clock0 => ram_block3a16.CLK0 
clock0 => ram_block3a17.CLK0 
clock0 => ram_block3a18.CLK0 
clock0 => ram_block3a19.CLK0 
clock0 => ram_block3a20.CLK0 
clock0 => ram_block3a21.CLK0 
clock0 => ram_block3a22.CLK0 
clock0 => ram_block3a23.CLK0 
clock0 => ram_block3a24.CLK0 
clock0 => ram_block3a25.CLK0 
clock0 => ram_block3a26.CLK0 
clock0 => ram_block3a27.CLK0 
clock0 => ram_block3a28.CLK0 
clock0 => ram_block3a29.CLK0 
clock0 => ram_block3a30.CLK0 
clock0 => ram_block3a31.CLK0 
clock1 => ram_block3a0.CLK1 
clock1 => ram_block3a1.CLK1 
clock1 => ram_block3a2.CLK1 
clock1 => ram_block3a3.CLK1 
clock1 => ram_block3a4.CLK1 
clock1 => ram_block3a5.CLK1 
clock1 => ram_block3a6.CLK1 
clock1 => ram_block3a7.CLK1 
clock1 => ram_block3a8.CLK1 
clock1 => ram_block3a9.CLK1 
clock1 => ram_block3a10.CLK1 
clock1 => ram_block3a11.CLK1 
clock1 => ram_block3a12.CLK1 
clock1 => ram_block3a13.CLK1 
clock1 => ram_block3a14.CLK1 
clock1 => ram_block3a15.CLK1 
clock1 => ram_block3a16.CLK1 
clock1 => ram_block3a17.CLK1 
clock1 => ram_block3a18.CLK1 
clock1 => ram_block3a19.CLK1 
clock1 => ram_block3a20.CLK1 
clock1 => ram_block3a21.CLK1 
clock1 => ram_block3a22.CLK1 
clock1 => ram_block3a23.CLK1 
clock1 => ram_block3a24.CLK1 
clock1 => ram_block3a25.CLK1 
clock1 => ram_block3a26.CLK1 
clock1 => ram_block3a27.CLK1 
clock1 => ram_block3a28.CLK1 
clock1 => ram_block3a29.CLK1 
clock1 => ram_block3a30.CLK1 
clock1 => ram_block3a31.CLK1 
data_a[0] => ram_block3a0.PORTADATAIN 
data_a[1] => ram_block3a1.PORTADATAIN 
data_a[2] => ram_block3a2.PORTADATAIN 
data_a[3] => ram_block3a3.PORTADATAIN 
data_a[4] => ram_block3a4.PORTADATAIN 
data_a[5] => ram_block3a5.PORTADATAIN 
data_a[6] => ram_block3a6.PORTADATAIN 
data_a[7] => ram_block3a7.PORTADATAIN 
data_a[8] => ram_block3a8.PORTADATAIN 
data_a[9] => ram_block3a9.PORTADATAIN 
data_a[10] => ram_block3a10.PORTADATAIN 
data_a[11] => ram_block3a11.PORTADATAIN 
data_a[12] => ram_block3a12.PORTADATAIN 
data_a[13] => ram_block3a13.PORTADATAIN 
data_a[14] => ram_block3a14.PORTADATAIN 
data_a[15] => ram_block3a15.PORTADATAIN 
data_a[16] => ram_block3a16.PORTADATAIN 
data_a[17] => ram_block3a17.PORTADATAIN 
data_a[18] => ram_block3a18.PORTADATAIN 
data_a[19] => ram_block3a19.PORTADATAIN 
data_a[20] => ram_block3a20.PORTADATAIN 
data_a[21] => ram_block3a21.PORTADATAIN 
data_a[22] => ram_block3a22.PORTADATAIN 
data_a[23] => ram_block3a23.PORTADATAIN 
data_a[24] => ram_block3a24.PORTADATAIN 
data_a[25] => ram_block3a25.PORTADATAIN 
data_a[26] => ram_block3a26.PORTADATAIN 
data_a[27] => ram_block3a27.PORTADATAIN 
data_a[28] => ram_block3a28.PORTADATAIN 
data_a[29] => ram_block3a29.PORTADATAIN 
data_a[30] => ram_block3a30.PORTADATAIN 
data_a[31] => ram_block3a31.PORTADATAIN 
data_b[0] => ram_block3a0.PORTBDATAIN 
data_b[1] => ram_block3a1.PORTBDATAIN 
data_b[2] => ram_block3a2.PORTBDATAIN 
data_b[3] => ram_block3a3.PORTBDATAIN 
data_b[4] => ram_block3a4.PORTBDATAIN 
data_b[5] => ram_block3a5.PORTBDATAIN 
data_b[6] => ram_block3a6.PORTBDATAIN 
data_b[7] => ram_block3a7.PORTBDATAIN 
data_b[8] => ram_block3a8.PORTBDATAIN 
data_b[9] => ram_block3a9.PORTBDATAIN 
data_b[10] => ram_block3a10.PORTBDATAIN 
data_b[11] => ram_block3a11.PORTBDATAIN 
data_b[12] => ram_block3a12.PORTBDATAIN 
data_b[13] => ram_block3a13.PORTBDATAIN 
data_b[14] => ram_block3a14.PORTBDATAIN 
data_b[15] => ram_block3a15.PORTBDATAIN 
data_b[16] => ram_block3a16.PORTBDATAIN 
data_b[17] => ram_block3a17.PORTBDATAIN 
data_b[18] => ram_block3a18.PORTBDATAIN 
data_b[19] => ram_block3a19.PORTBDATAIN 
data_b[20] => ram_block3a20.PORTBDATAIN 
data_b[21] => ram_block3a21.PORTBDATAIN 
data_b[22] => ram_block3a22.PORTBDATAIN 
data_b[23] => ram_block3a23.PORTBDATAIN 
data_b[24] => ram_block3a24.PORTBDATAIN 
data_b[25] => ram_block3a25.PORTBDATAIN 
data_b[26] => ram_block3a26.PORTBDATAIN 
data_b[27] => ram_block3a27.PORTBDATAIN 
data_b[28] => ram_block3a28.PORTBDATAIN 
data_b[29] => ram_block3a29.PORTBDATAIN 
data_b[30] => ram_block3a30.PORTBDATAIN 
data_b[31] => ram_block3a31.PORTBDATAIN 
q_a[0] <= ram_block3a0.PORTADATAOUT 
q_a[1] <= ram_block3a1.PORTADATAOUT 
q_a[2] <= ram_block3a2.PORTADATAOUT 
q_a[3] <= ram_block3a3.PORTADATAOUT 
q_a[4] <= ram_block3a4.PORTADATAOUT 
q_a[5] <= ram_block3a5.PORTADATAOUT 
q_a[6] <= ram_block3a6.PORTADATAOUT 
q_a[7] <= ram_block3a7.PORTADATAOUT 
q_a[8] <= ram_block3a8.PORTADATAOUT 
q_a[9] <= ram_block3a9.PORTADATAOUT 
q_a[10] <= ram_block3a10.PORTADATAOUT 
q_a[11] <= ram_block3a11.PORTADATAOUT 
q_a[12] <= ram_block3a12.PORTADATAOUT 
q_a[13] <= ram_block3a13.PORTADATAOUT 
q_a[14] <= ram_block3a14.PORTADATAOUT 
q_a[15] <= ram_block3a15.PORTADATAOUT 
q_a[16] <= ram_block3a16.PORTADATAOUT 
q_a[17] <= ram_block3a17.PORTADATAOUT 
q_a[18] <= ram_block3a18.PORTADATAOUT 
q_a[19] <= ram_block3a19.PORTADATAOUT 
q_a[20] <= ram_block3a20.PORTADATAOUT 
q_a[21] <= ram_block3a21.PORTADATAOUT 
q_a[22] <= ram_block3a22.PORTADATAOUT 
q_a[23] <= ram_block3a23.PORTADATAOUT 
q_a[24] <= ram_block3a24.PORTADATAOUT 
q_a[25] <= ram_block3a25.PORTADATAOUT 
q_a[26] <= ram_block3a26.PORTADATAOUT 
q_a[27] <= ram_block3a27.PORTADATAOUT 
q_a[28] <= ram_block3a28.PORTADATAOUT 
q_a[29] <= ram_block3a29.PORTADATAOUT 
q_a[30] <= ram_block3a30.PORTADATAOUT 
q_a[31] <= ram_block3a31.PORTADATAOUT 
q_b[0] <= ram_block3a0.PORTBDATAOUT 
q_b[1] <= ram_block3a1.PORTBDATAOUT 
q_b[2] <= ram_block3a2.PORTBDATAOUT 
q_b[3] <= ram_block3a3.PORTBDATAOUT 
q_b[4] <= ram_block3a4.PORTBDATAOUT 
q_b[5] <= ram_block3a5.PORTBDATAOUT 
q_b[6] <= ram_block3a6.PORTBDATAOUT 
q_b[7] <= ram_block3a7.PORTBDATAOUT 
q_b[8] <= ram_block3a8.PORTBDATAOUT 
q_b[9] <= ram_block3a9.PORTBDATAOUT 
q_b[10] <= ram_block3a10.PORTBDATAOUT 
q_b[11] <= ram_block3a11.PORTBDATAOUT 
q_b[12] <= ram_block3a12.PORTBDATAOUT 
q_b[13] <= ram_block3a13.PORTBDATAOUT 
q_b[14] <= ram_block3a14.PORTBDATAOUT 
q_b[15] <= ram_block3a15.PORTBDATAOUT 
q_b[16] <= ram_block3a16.PORTBDATAOUT 
q_b[17] <= ram_block3a17.PORTBDATAOUT 
q_b[18] <= ram_block3a18.PORTBDATAOUT 
q_b[19] <= ram_block3a19.PORTBDATAOUT 
q_b[20] <= ram_block3a20.PORTBDATAOUT 
q_b[21] <= ram_block3a21.PORTBDATAOUT 
q_b[22] <= ram_block3a22.PORTBDATAOUT 
q_b[23] <= ram_block3a23.PORTBDATAOUT 
q_b[24] <= ram_block3a24.PORTBDATAOUT 
q_b[25] <= ram_block3a25.PORTBDATAOUT 
q_b[26] <= ram_block3a26.PORTBDATAOUT 
q_b[27] <= ram_block3a27.PORTBDATAOUT 
q_b[28] <= ram_block3a28.PORTBDATAOUT 
q_b[29] <= ram_block3a29.PORTBDATAOUT 
q_b[30] <= ram_block3a30.PORTBDATAOUT 
q_b[31] <= ram_block3a31.PORTBDATAOUT 
wren_a => ram_block3a0.PORTAWE 
wren_a => ram_block3a1.PORTAWE 
wren_a => ram_block3a2.PORTAWE 
wren_a => ram_block3a3.PORTAWE 
wren_a => ram_block3a4.PORTAWE 
wren_a => ram_block3a5.PORTAWE 
wren_a => ram_block3a6.PORTAWE 
wren_a => ram_block3a7.PORTAWE 
wren_a => ram_block3a8.PORTAWE 
wren_a => ram_block3a9.PORTAWE 
wren_a => ram_block3a10.PORTAWE 
wren_a => ram_block3a11.PORTAWE 
wren_a => ram_block3a12.PORTAWE 
wren_a => ram_block3a13.PORTAWE 
wren_a => ram_block3a14.PORTAWE 
wren_a => ram_block3a15.PORTAWE 
wren_a => ram_block3a16.PORTAWE 
wren_a => ram_block3a17.PORTAWE 
wren_a => ram_block3a18.PORTAWE 
wren_a => ram_block3a19.PORTAWE 
wren_a => ram_block3a20.PORTAWE 
wren_a => ram_block3a21.PORTAWE 
wren_a => ram_block3a22.PORTAWE 
wren_a => ram_block3a23.PORTAWE 
wren_a => ram_block3a24.PORTAWE 
wren_a => ram_block3a25.PORTAWE 
wren_a => ram_block3a26.PORTAWE 
wren_a => ram_block3a27.PORTAWE 
wren_a => ram_block3a28.PORTAWE 
wren_a => ram_block3a29.PORTAWE 
wren_a => ram_block3a30.PORTAWE 
wren_a => ram_block3a31.PORTAWE 
wren_b => ram_block3a0.PORTBRE 
wren_b => ram_block3a1.PORTBRE 
wren_b => ram_block3a2.PORTBRE 
wren_b => ram_block3a3.PORTBRE 
wren_b => ram_block3a4.PORTBRE 
wren_b => ram_block3a5.PORTBRE 
wren_b => ram_block3a6.PORTBRE 
wren_b => ram_block3a7.PORTBRE 
wren_b => ram_block3a8.PORTBRE 
wren_b => ram_block3a9.PORTBRE 
wren_b => ram_block3a10.PORTBRE 
wren_b => ram_block3a11.PORTBRE 
wren_b => ram_block3a12.PORTBRE 
wren_b => ram_block3a13.PORTBRE 
wren_b => ram_block3a14.PORTBRE 
wren_b => ram_block3a15.PORTBRE 
wren_b => ram_block3a16.PORTBRE 
wren_b => ram_block3a17.PORTBRE 
wren_b => ram_block3a18.PORTBRE 
wren_b => ram_block3a19.PORTBRE 
wren_b => ram_block3a20.PORTBRE 
wren_b => ram_block3a21.PORTBRE 
wren_b => ram_block3a22.PORTBRE 
wren_b => ram_block3a23.PORTBRE 
wren_b => ram_block3a24.PORTBRE 
wren_b => ram_block3a25.PORTBRE 
wren_b => ram_block3a26.PORTBRE 
wren_b => ram_block3a27.PORTBRE 
wren_b => ram_block3a28.PORTBRE 
wren_b => ram_block3a29.PORTBRE 
wren_b => ram_block3a30.PORTBRE 
wren_b => ram_block3a31.PORTBRE 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4|program_mem:Mem_inst|altsyncram:altsyncram_component|altsyncram_vnk1:auto_generated|sld_mod_ram_rom:mgl_prim2 
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE 
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE 
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE 
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE 
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE 
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE 
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE 
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE 
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE 
enable_write <= enable_write.DB_MAX_OUTPUT_PORT_TYPE 
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE 
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE 
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE 
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE 
data_write[4] <= ram_rom_data_reg[4].DB_MAX_OUTPUT_PORT_TYPE 
data_write[5] <= ram_rom_data_reg[5].DB_MAX_OUTPUT_PORT_TYPE 
data_write[6] <= ram_rom_data_reg[6].DB_MAX_OUTPUT_PORT_TYPE 
data_write[7] <= ram_rom_data_reg[7].DB_MAX_OUTPUT_PORT_TYPE 
data_write[8] <= ram_rom_data_reg[8].DB_MAX_OUTPUT_PORT_TYPE 
data_write[9] <= ram_rom_data_reg[9].DB_MAX_OUTPUT_PORT_TYPE 
data_write[10] <= ram_rom_data_reg[10].DB_MAX_OUTPUT_PORT_TYPE 
data_write[11] <= ram_rom_data_reg[11].DB_MAX_OUTPUT_PORT_TYPE 
data_write[12] <= ram_rom_data_reg[12].DB_MAX_OUTPUT_PORT_TYPE 
data_write[13] <= ram_rom_data_reg[13].DB_MAX_OUTPUT_PORT_TYPE 
data_write[14] <= ram_rom_data_reg[14].DB_MAX_OUTPUT_PORT_TYPE 
data_write[15] <= ram_rom_data_reg[15].DB_MAX_OUTPUT_PORT_TYPE 
data_write[16] <= ram_rom_data_reg[16].DB_MAX_OUTPUT_PORT_TYPE 
data_write[17] <= ram_rom_data_reg[17].DB_MAX_OUTPUT_PORT_TYPE 
data_write[18] <= ram_rom_data_reg[18].DB_MAX_OUTPUT_PORT_TYPE 
data_write[19] <= ram_rom_data_reg[19].DB_MAX_OUTPUT_PORT_TYPE 
data_write[20] <= ram_rom_data_reg[20].DB_MAX_OUTPUT_PORT_TYPE 
data_write[21] <= ram_rom_data_reg[21].DB_MAX_OUTPUT_PORT_TYPE 
data_write[22] <= ram_rom_data_reg[22].DB_MAX_OUTPUT_PORT_TYPE 
data_write[23] <= ram_rom_data_reg[23].DB_MAX_OUTPUT_PORT_TYPE 
data_write[24] <= ram_rom_data_reg[24].DB_MAX_OUTPUT_PORT_TYPE 
data_write[25] <= ram_rom_data_reg[25].DB_MAX_OUTPUT_PORT_TYPE 
data_write[26] <= ram_rom_data_reg[26].DB_MAX_OUTPUT_PORT_TYPE 
data_write[27] <= ram_rom_data_reg[27].DB_MAX_OUTPUT_PORT_TYPE 
data_write[28] <= ram_rom_data_reg[28].DB_MAX_OUTPUT_PORT_TYPE 
data_write[29] <= ram_rom_data_reg[29].DB_MAX_OUTPUT_PORT_TYPE 
data_write[30] <= ram_rom_data_reg[30].DB_MAX_OUTPUT_PORT_TYPE 
data_write[31] <= ram_rom_data_reg[31].DB_MAX_OUTPUT_PORT_TYPE 
data_read[0] => ram_rom_data_reg.DATAB 
data_read[1] => ram_rom_data_reg.DATAB 
data_read[2] => ram_rom_data_reg.DATAB 
data_read[3] => ram_rom_data_reg.DATAB 
data_read[4] => ram_rom_data_reg.DATAB 
data_read[5] => ram_rom_data_reg.DATAB 
data_read[6] => ram_rom_data_reg.DATAB 
data_read[7] => ram_rom_data_reg.DATAB 
data_read[8] => ram_rom_data_reg.DATAB 
data_read[9] => ram_rom_data_reg.DATAB 
data_read[10] => ram_rom_data_reg.DATAB 
data_read[11] => ram_rom_data_reg.DATAB 
data_read[12] => ram_rom_data_reg.DATAB 
data_read[13] => ram_rom_data_reg.DATAB 
data_read[14] => ram_rom_data_reg.DATAB 
data_read[15] => ram_rom_data_reg.DATAB 
data_read[16] => ram_rom_data_reg.DATAB 
data_read[17] => ram_rom_data_reg.DATAB 
data_read[18] => ram_rom_data_reg.DATAB 
data_read[19] => ram_rom_data_reg.DATAB 
data_read[20] => ram_rom_data_reg.DATAB 
data_read[21] => ram_rom_data_reg.DATAB 
data_read[22] => ram_rom_data_reg.DATAB 
data_read[23] => ram_rom_data_reg.DATAB 
data_read[24] => ram_rom_data_reg.DATAB 
data_read[25] => ram_rom_data_reg.DATAB 
data_read[26] => ram_rom_data_reg.DATAB 
data_read[27] => ram_rom_data_reg.DATAB 
data_read[28] => ram_rom_data_reg.DATAB 
data_read[29] => ram_rom_data_reg.DATAB 
data_read[30] => ram_rom_data_reg.DATAB 
data_read[31] => ram_rom_data_reg.DATAB 
raw_tck => is_in_use_reg.CLK 
raw_tck => bypass_reg_out.CLK 
raw_tck => ir_loaded_address_reg[0].CLK 
raw_tck => ir_loaded_address_reg[1].CLK 
raw_tck => ir_loaded_address_reg[2].CLK 
raw_tck => ir_loaded_address_reg[3].CLK 
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK 
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK 
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK 
raw_tck => ram_rom_data_shift_cntr_reg[3].CLK 
raw_tck => ram_rom_data_shift_cntr_reg[4].CLK 
raw_tck => ram_rom_data_shift_cntr_reg[5].CLK 
raw_tck => ram_rom_data_reg[0].CLK 
raw_tck => ram_rom_data_reg[1].CLK 
raw_tck => ram_rom_data_reg[2].CLK 
raw_tck => ram_rom_data_reg[3].CLK 
raw_tck => ram_rom_data_reg[4].CLK 
raw_tck => ram_rom_data_reg[5].CLK 
raw_tck => ram_rom_data_reg[6].CLK 
raw_tck => ram_rom_data_reg[7].CLK 
raw_tck => ram_rom_data_reg[8].CLK 
raw_tck => ram_rom_data_reg[9].CLK 
raw_tck => ram_rom_data_reg[10].CLK 
raw_tck => ram_rom_data_reg[11].CLK 
raw_tck => ram_rom_data_reg[12].CLK 
raw_tck => ram_rom_data_reg[13].CLK 
raw_tck => ram_rom_data_reg[14].CLK 
raw_tck => ram_rom_data_reg[15].CLK 
raw_tck => ram_rom_data_reg[16].CLK 
raw_tck => ram_rom_data_reg[17].CLK 
raw_tck => ram_rom_data_reg[18].CLK 
raw_tck => ram_rom_data_reg[19].CLK 
raw_tck => ram_rom_data_reg[20].CLK 
raw_tck => ram_rom_data_reg[21].CLK 
raw_tck => ram_rom_data_reg[22].CLK 
raw_tck => ram_rom_data_reg[23].CLK 
raw_tck => ram_rom_data_reg[24].CLK 
raw_tck => ram_rom_data_reg[25].CLK 
raw_tck => ram_rom_data_reg[26].CLK 
raw_tck => ram_rom_data_reg[27].CLK 
raw_tck => ram_rom_data_reg[28].CLK 
raw_tck => ram_rom_data_reg[29].CLK 
raw_tck => ram_rom_data_reg[30].CLK 
raw_tck => ram_rom_data_reg[31].CLK 
raw_tck => ram_rom_addr_reg[0].CLK 
raw_tck => ram_rom_addr_reg[1].CLK 
raw_tck => ram_rom_addr_reg[2].CLK 
raw_tck => ram_rom_addr_reg[3].CLK 
raw_tck => ram_rom_addr_reg[4].CLK 
raw_tck => ram_rom_addr_reg[5].CLK 
raw_tck => ram_rom_addr_reg[6].CLK 
raw_tck => ram_rom_addr_reg[7].CLK 
raw_tck => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TCK 
raw_tck => tck_usr.DATAIN 
tdi => ram_rom_addr_reg.DATAB 
tdi => ram_rom_data_reg.DATAB 
tdi => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TDI 
tdi => bypass_reg_out.DATAIN 
usr1 => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.USR1 
usr1 => dr_scan.IN0 
usr1 => name_gen.IN0 
jtag_state_cdr => name_gen.IN0 
jtag_state_sdr => sdr.IN1 
jtag_state_sdr => name_gen.IN1 
jtag_state_sdr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.SHIFT 
jtag_state_e1dr => ram_rom_update_write_ena.IN1 
jtag_state_udr => udr.IN1 
jtag_state_udr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.UPDATE 
jtag_state_uir => ~NO_FANOUT~ 
clr => is_in_use_reg.ACLR 
clr => bypass_reg_out.ACLR 
ena => dr_scan.IN1 
ena => name_gen.IN1 
ena => bypass_reg_out.ENA 
ir_in[0] => process_0.IN0 
ir_in[0] => tdo.OUTPUTSELECT 
ir_in[0] => is_in_use_reg.OUTPUTSELECT 
ir_in[0] => ram_rom_addr_reg[0].ACLR 
ir_in[0] => ram_rom_addr_reg[1].ACLR 
ir_in[0] => ram_rom_addr_reg[2].ACLR 
ir_in[0] => ram_rom_addr_reg[3].ACLR 
ir_in[0] => ram_rom_addr_reg[4].ACLR 
ir_in[0] => ram_rom_addr_reg[5].ACLR 
ir_in[0] => ram_rom_addr_reg[6].ACLR 
ir_in[0] => ram_rom_addr_reg[7].ACLR 
ir_in[1] => process_0.IN1 
ir_in[1] => process_0.IN0 
ir_in[1] => ram_rom_incr_addr.IN1 
ir_in[2] => process_0.IN1 
ir_in[2] => ram_rom_incr_addr.IN1 
ir_in[2] => enable_write.IN1 
ir_in[3] => process_0.IN1 
ir_in[3] => process_0.IN1 
ir_in[3] => process_0.IN1 
ir_in[3] => ram_rom_data_shift_cntr_reg[0].ACLR 
ir_in[3] => ram_rom_data_shift_cntr_reg[1].ACLR 
ir_in[3] => ram_rom_data_shift_cntr_reg[2].ACLR 
ir_in[3] => ram_rom_data_shift_cntr_reg[3].ACLR 
ir_in[3] => ram_rom_data_shift_cntr_reg[4].ACLR 
ir_in[3] => ram_rom_data_shift_cntr_reg[5].ACLR 
ir_in[4] => process_0.IN1 
ir_in[4] => is_in_use_reg.OUTPUTSELECT 
ir_out[0] <= is_in_use_reg.DB_MAX_OUTPUT_PORT_TYPE 
ir_out[1] <= ir_loaded_address_reg[0].DB_MAX_OUTPUT_PORT_TYPE 
ir_out[2] <= ir_loaded_address_reg[1].DB_MAX_OUTPUT_PORT_TYPE 
ir_out[3] <= ir_loaded_address_reg[2].DB_MAX_OUTPUT_PORT_TYPE 
ir_out[4] <= ir_loaded_address_reg[3].DB_MAX_OUTPUT_PORT_TYPE 
tdo <= tdo.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4|program_mem:Mem_inst|altsyncram:altsyncram_component|altsyncram_vnk1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr 
ROM_DATA[0] => Mux3.IN131 
ROM_DATA[1] => Mux2.IN131 
ROM_DATA[2] => Mux1.IN131 
ROM_DATA[3] => Mux0.IN131 
ROM_DATA[4] => Mux3.IN127 
ROM_DATA[5] => Mux2.IN127 
ROM_DATA[6] => Mux1.IN127 
ROM_DATA[7] => Mux0.IN127 
ROM_DATA[8] => Mux3.IN123 
ROM_DATA[9] => Mux2.IN123 
ROM_DATA[10] => Mux1.IN123 
ROM_DATA[11] => Mux0.IN123 
ROM_DATA[12] => Mux3.IN119 
ROM_DATA[13] => Mux2.IN119 
ROM_DATA[14] => Mux1.IN119 
ROM_DATA[15] => Mux0.IN119 
ROM_DATA[16] => Mux3.IN115 
ROM_DATA[17] => Mux2.IN115 
ROM_DATA[18] => Mux1.IN115 
ROM_DATA[19] => Mux0.IN115 
ROM_DATA[20] => Mux3.IN111 
ROM_DATA[21] => Mux2.IN111 
ROM_DATA[22] => Mux1.IN111 
ROM_DATA[23] => Mux0.IN111 
ROM_DATA[24] => Mux3.IN107 
ROM_DATA[25] => Mux2.IN107 
ROM_DATA[26] => Mux1.IN107 
ROM_DATA[27] => Mux0.IN107 
ROM_DATA[28] => Mux3.IN103 
ROM_DATA[29] => Mux2.IN103 
ROM_DATA[30] => Mux1.IN103 
ROM_DATA[31] => Mux0.IN103 
ROM_DATA[32] => Mux3.IN99 
ROM_DATA[33] => Mux2.IN99 
ROM_DATA[34] => Mux1.IN99 
ROM_DATA[35] => Mux0.IN99 
ROM_DATA[36] => Mux3.IN95 
ROM_DATA[37] => Mux2.IN95 
ROM_DATA[38] => Mux1.IN95 
ROM_DATA[39] => Mux0.IN95 
ROM_DATA[40] => Mux3.IN91 
ROM_DATA[41] => Mux2.IN91 
ROM_DATA[42] => Mux1.IN91 
ROM_DATA[43] => Mux0.IN91 
ROM_DATA[44] => Mux3.IN87 
ROM_DATA[45] => Mux2.IN87 
ROM_DATA[46] => Mux1.IN87 
ROM_DATA[47] => Mux0.IN87 
ROM_DATA[48] => Mux3.IN83 
ROM_DATA[49] => Mux2.IN83 
ROM_DATA[50] => Mux1.IN83 
ROM_DATA[51] => Mux0.IN83 
ROM_DATA[52] => Mux3.IN79 
ROM_DATA[53] => Mux2.IN79 
ROM_DATA[54] => Mux1.IN79 
ROM_DATA[55] => Mux0.IN79 
ROM_DATA[56] => Mux3.IN75 
ROM_DATA[57] => Mux2.IN75 
ROM_DATA[58] => Mux1.IN75 
ROM_DATA[59] => Mux0.IN75 
ROM_DATA[60] => Mux3.IN71 
ROM_DATA[61] => Mux2.IN71 
ROM_DATA[62] => Mux1.IN71 
ROM_DATA[63] => Mux0.IN71 
ROM_DATA[64] => Mux3.IN67 
ROM_DATA[65] => Mux2.IN67 
ROM_DATA[66] => Mux1.IN67 
ROM_DATA[67] => Mux0.IN67 
ROM_DATA[68] => Mux3.IN63 
ROM_DATA[69] => Mux2.IN63 
ROM_DATA[70] => Mux1.IN63 
ROM_DATA[71] => Mux0.IN63 
ROM_DATA[72] => Mux3.IN59 
ROM_DATA[73] => Mux2.IN59 
ROM_DATA[74] => Mux1.IN59 
ROM_DATA[75] => Mux0.IN59 
ROM_DATA[76] => Mux3.IN55 
ROM_DATA[77] => Mux2.IN55 
ROM_DATA[78] => Mux1.IN55 
ROM_DATA[79] => Mux0.IN55 
TCK => WORD_SR[0].CLK 
TCK => WORD_SR[1].CLK 
TCK => WORD_SR[2].CLK 
TCK => WORD_SR[3].CLK 
TCK => word_counter[0].CLK 
TCK => word_counter[1].CLK 
TCK => word_counter[2].CLK 
TCK => word_counter[3].CLK 
TCK => word_counter[4].CLK 
SHIFT => word_counter.OUTPUTSELECT 
SHIFT => word_counter.OUTPUTSELECT 
SHIFT => word_counter.OUTPUTSELECT 
SHIFT => word_counter.OUTPUTSELECT 
SHIFT => word_counter.OUTPUTSELECT 
SHIFT => WORD_SR.OUTPUTSELECT 
SHIFT => WORD_SR.OUTPUTSELECT 
SHIFT => WORD_SR.OUTPUTSELECT 
SHIFT => WORD_SR.OUTPUTSELECT 
UPDATE => clear_signal.IN0 
USR1 => clear_signal.IN1 
ENA => word_counter.OUTPUTSELECT 
ENA => word_counter.OUTPUTSELECT 
ENA => word_counter.OUTPUTSELECT 
ENA => word_counter.OUTPUTSELECT 
ENA => word_counter.OUTPUTSELECT 
ENA => WORD_SR.OUTPUTSELECT 
ENA => WORD_SR.OUTPUTSELECT 
ENA => WORD_SR.OUTPUTSELECT 
ENA => WORD_SR.OUTPUTSELECT 
TDI => WORD_SR.DATAA 
TDO <= WORD_SR[0].DB_MAX_OUTPUT_PORT_TYPE 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4|Adder:Reg_add 
dataa[0] => lpm_add_sub:lpm_add_sub_component.dataa[0] 
dataa[1] => lpm_add_sub:lpm_add_sub_component.dataa[1] 
dataa[2] => lpm_add_sub:lpm_add_sub_component.dataa[2] 
dataa[3] => lpm_add_sub:lpm_add_sub_component.dataa[3] 
dataa[4] => lpm_add_sub:lpm_add_sub_component.dataa[4] 
dataa[5] => lpm_add_sub:lpm_add_sub_component.dataa[5] 
dataa[6] => lpm_add_sub:lpm_add_sub_component.dataa[6] 
dataa[7] => lpm_add_sub:lpm_add_sub_component.dataa[7] 
dataa[8] => lpm_add_sub:lpm_add_sub_component.dataa[8] 
dataa[9] => lpm_add_sub:lpm_add_sub_component.dataa[9] 
dataa[10] => lpm_add_sub:lpm_add_sub_component.dataa[10] 
dataa[11] => lpm_add_sub:lpm_add_sub_component.dataa[11] 
dataa[12] => lpm_add_sub:lpm_add_sub_component.dataa[12] 
dataa[13] => lpm_add_sub:lpm_add_sub_component.dataa[13] 
dataa[14] => lpm_add_sub:lpm_add_sub_component.dataa[14] 
dataa[15] => lpm_add_sub:lpm_add_sub_component.dataa[15] 
dataa[16] => lpm_add_sub:lpm_add_sub_component.dataa[16] 
dataa[17] => lpm_add_sub:lpm_add_sub_component.dataa[17] 
dataa[18] => lpm_add_sub:lpm_add_sub_component.dataa[18] 
dataa[19] => lpm_add_sub:lpm_add_sub_component.dataa[19] 
dataa[20] => lpm_add_sub:lpm_add_sub_component.dataa[20] 
dataa[21] => lpm_add_sub:lpm_add_sub_component.dataa[21] 
dataa[22] => lpm_add_sub:lpm_add_sub_component.dataa[22] 
dataa[23] => lpm_add_sub:lpm_add_sub_component.dataa[23] 
dataa[24] => lpm_add_sub:lpm_add_sub_component.dataa[24] 
dataa[25] => lpm_add_sub:lpm_add_sub_component.dataa[25] 
dataa[26] => lpm_add_sub:lpm_add_sub_component.dataa[26] 
dataa[27] => lpm_add_sub:lpm_add_sub_component.dataa[27] 
dataa[28] => lpm_add_sub:lpm_add_sub_component.dataa[28] 
dataa[29] => lpm_add_sub:lpm_add_sub_component.dataa[29] 
dataa[30] => lpm_add_sub:lpm_add_sub_component.dataa[30] 
dataa[31] => lpm_add_sub:lpm_add_sub_component.dataa[31] 
datab[0] => lpm_add_sub:lpm_add_sub_component.datab[0] 
datab[1] => lpm_add_sub:lpm_add_sub_component.datab[1] 
datab[2] => lpm_add_sub:lpm_add_sub_component.datab[2] 
datab[3] => lpm_add_sub:lpm_add_sub_component.datab[3] 
datab[4] => lpm_add_sub:lpm_add_sub_component.datab[4] 
datab[5] => lpm_add_sub:lpm_add_sub_component.datab[5] 
datab[6] => lpm_add_sub:lpm_add_sub_component.datab[6] 
datab[7] => lpm_add_sub:lpm_add_sub_component.datab[7] 
datab[8] => lpm_add_sub:lpm_add_sub_component.datab[8] 
datab[9] => lpm_add_sub:lpm_add_sub_component.datab[9] 
datab[10] => lpm_add_sub:lpm_add_sub_component.datab[10] 
datab[11] => lpm_add_sub:lpm_add_sub_component.datab[11] 
datab[12] => lpm_add_sub:lpm_add_sub_component.datab[12] 
datab[13] => lpm_add_sub:lpm_add_sub_component.datab[13] 
datab[14] => lpm_add_sub:lpm_add_sub_component.datab[14] 
datab[15] => lpm_add_sub:lpm_add_sub_component.datab[15] 
datab[16] => lpm_add_sub:lpm_add_sub_component.datab[16] 
datab[17] => lpm_add_sub:lpm_add_sub_component.datab[17] 
datab[18] => lpm_add_sub:lpm_add_sub_component.datab[18] 
datab[19] => lpm_add_sub:lpm_add_sub_component.datab[19] 
datab[20] => lpm_add_sub:lpm_add_sub_component.datab[20] 
datab[21] => lpm_add_sub:lpm_add_sub_component.datab[21] 
datab[22] => lpm_add_sub:lpm_add_sub_component.datab[22] 
datab[23] => lpm_add_sub:lpm_add_sub_component.datab[23] 
datab[24] => lpm_add_sub:lpm_add_sub_component.datab[24] 
datab[25] => lpm_add_sub:lpm_add_sub_component.datab[25] 
datab[26] => lpm_add_sub:lpm_add_sub_component.datab[26] 
datab[27] => lpm_add_sub:lpm_add_sub_component.datab[27] 
datab[28] => lpm_add_sub:lpm_add_sub_component.datab[28] 
datab[29] => lpm_add_sub:lpm_add_sub_component.datab[29] 
datab[30] => lpm_add_sub:lpm_add_sub_component.datab[30] 
datab[31] => lpm_add_sub:lpm_add_sub_component.datab[31] 
result[0] <= lpm_add_sub:lpm_add_sub_component.result[0] 
result[1] <= lpm_add_sub:lpm_add_sub_component.result[1] 
result[2] <= lpm_add_sub:lpm_add_sub_component.result[2] 
result[3] <= lpm_add_sub:lpm_add_sub_component.result[3] 
result[4] <= lpm_add_sub:lpm_add_sub_component.result[4] 
result[5] <= lpm_add_sub:lpm_add_sub_component.result[5] 
result[6] <= lpm_add_sub:lpm_add_sub_component.result[6] 
result[7] <= lpm_add_sub:lpm_add_sub_component.result[7] 
result[8] <= lpm_add_sub:lpm_add_sub_component.result[8] 
result[9] <= lpm_add_sub:lpm_add_sub_component.result[9] 
result[10] <= lpm_add_sub:lpm_add_sub_component.result[10] 
result[11] <= lpm_add_sub:lpm_add_sub_component.result[11] 
result[12] <= lpm_add_sub:lpm_add_sub_component.result[12] 
result[13] <= lpm_add_sub:lpm_add_sub_component.result[13] 
result[14] <= lpm_add_sub:lpm_add_sub_component.result[14] 
result[15] <= lpm_add_sub:lpm_add_sub_component.result[15] 
result[16] <= lpm_add_sub:lpm_add_sub_component.result[16] 
result[17] <= lpm_add_sub:lpm_add_sub_component.result[17] 
result[18] <= lpm_add_sub:lpm_add_sub_component.result[18] 
result[19] <= lpm_add_sub:lpm_add_sub_component.result[19] 
result[20] <= lpm_add_sub:lpm_add_sub_component.result[20] 
result[21] <= lpm_add_sub:lpm_add_sub_component.result[21] 
result[22] <= lpm_add_sub:lpm_add_sub_component.result[22] 
result[23] <= lpm_add_sub:lpm_add_sub_component.result[23] 
result[24] <= lpm_add_sub:lpm_add_sub_component.result[24] 
result[25] <= lpm_add_sub:lpm_add_sub_component.result[25] 
result[26] <= lpm_add_sub:lpm_add_sub_component.result[26] 
result[27] <= lpm_add_sub:lpm_add_sub_component.result[27] 
result[28] <= lpm_add_sub:lpm_add_sub_component.result[28] 
result[29] <= lpm_add_sub:lpm_add_sub_component.result[29] 
result[30] <= lpm_add_sub:lpm_add_sub_component.result[30] 
result[31] <= lpm_add_sub:lpm_add_sub_component.result[31] 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4|Adder:Reg_add|lpm_add_sub:lpm_add_sub_component 
dataa[0] => add_sub_2qe:auto_generated.dataa[0] 
dataa[1] => add_sub_2qe:auto_generated.dataa[1] 
dataa[2] => add_sub_2qe:auto_generated.dataa[2] 
dataa[3] => add_sub_2qe:auto_generated.dataa[3] 
dataa[4] => add_sub_2qe:auto_generated.dataa[4] 
dataa[5] => add_sub_2qe:auto_generated.dataa[5] 
dataa[6] => add_sub_2qe:auto_generated.dataa[6] 
dataa[7] => add_sub_2qe:auto_generated.dataa[7] 
dataa[8] => add_sub_2qe:auto_generated.dataa[8] 
dataa[9] => add_sub_2qe:auto_generated.dataa[9] 
dataa[10] => add_sub_2qe:auto_generated.dataa[10] 
dataa[11] => add_sub_2qe:auto_generated.dataa[11] 
dataa[12] => add_sub_2qe:auto_generated.dataa[12] 
dataa[13] => add_sub_2qe:auto_generated.dataa[13] 
dataa[14] => add_sub_2qe:auto_generated.dataa[14] 
dataa[15] => add_sub_2qe:auto_generated.dataa[15] 
dataa[16] => add_sub_2qe:auto_generated.dataa[16] 
dataa[17] => add_sub_2qe:auto_generated.dataa[17] 
dataa[18] => add_sub_2qe:auto_generated.dataa[18] 
dataa[19] => add_sub_2qe:auto_generated.dataa[19] 
dataa[20] => add_sub_2qe:auto_generated.dataa[20] 
dataa[21] => add_sub_2qe:auto_generated.dataa[21] 
dataa[22] => add_sub_2qe:auto_generated.dataa[22] 
dataa[23] => add_sub_2qe:auto_generated.dataa[23] 
dataa[24] => add_sub_2qe:auto_generated.dataa[24] 
dataa[25] => add_sub_2qe:auto_generated.dataa[25] 
dataa[26] => add_sub_2qe:auto_generated.dataa[26] 
dataa[27] => add_sub_2qe:auto_generated.dataa[27] 
dataa[28] => add_sub_2qe:auto_generated.dataa[28] 
dataa[29] => add_sub_2qe:auto_generated.dataa[29] 
dataa[30] => add_sub_2qe:auto_generated.dataa[30] 
dataa[31] => add_sub_2qe:auto_generated.dataa[31] 
datab[0] => add_sub_2qe:auto_generated.datab[0] 
datab[1] => add_sub_2qe:auto_generated.datab[1] 
datab[2] => add_sub_2qe:auto_generated.datab[2] 
datab[3] => add_sub_2qe:auto_generated.datab[3] 
datab[4] => add_sub_2qe:auto_generated.datab[4] 
datab[5] => add_sub_2qe:auto_generated.datab[5] 
datab[6] => add_sub_2qe:auto_generated.datab[6] 
datab[7] => add_sub_2qe:auto_generated.datab[7] 
datab[8] => add_sub_2qe:auto_generated.datab[8] 
datab[9] => add_sub_2qe:auto_generated.datab[9] 
datab[10] => add_sub_2qe:auto_generated.datab[10] 
datab[11] => add_sub_2qe:auto_generated.datab[11] 
datab[12] => add_sub_2qe:auto_generated.datab[12] 
datab[13] => add_sub_2qe:auto_generated.datab[13] 
datab[14] => add_sub_2qe:auto_generated.datab[14] 
datab[15] => add_sub_2qe:auto_generated.datab[15] 
datab[16] => add_sub_2qe:auto_generated.datab[16] 
datab[17] => add_sub_2qe:auto_generated.datab[17] 
datab[18] => add_sub_2qe:auto_generated.datab[18] 
datab[19] => add_sub_2qe:auto_generated.datab[19] 
datab[20] => add_sub_2qe:auto_generated.datab[20] 
datab[21] => add_sub_2qe:auto_generated.datab[21] 
datab[22] => add_sub_2qe:auto_generated.datab[22] 
datab[23] => add_sub_2qe:auto_generated.datab[23] 
datab[24] => add_sub_2qe:auto_generated.datab[24] 
datab[25] => add_sub_2qe:auto_generated.datab[25] 
datab[26] => add_sub_2qe:auto_generated.datab[26] 
datab[27] => add_sub_2qe:auto_generated.datab[27] 
datab[28] => add_sub_2qe:auto_generated.datab[28] 
datab[29] => add_sub_2qe:auto_generated.datab[29] 
datab[30] => add_sub_2qe:auto_generated.datab[30] 
datab[31] => add_sub_2qe:auto_generated.datab[31] 
cin => ~NO_FANOUT~ 
add_sub => ~NO_FANOUT~ 
clock => ~NO_FANOUT~ 
aclr => ~NO_FANOUT~ 
clken => ~NO_FANOUT~ 
result[0] <= add_sub_2qe:auto_generated.result[0] 
result[1] <= add_sub_2qe:auto_generated.result[1] 
result[2] <= add_sub_2qe:auto_generated.result[2] 
result[3] <= add_sub_2qe:auto_generated.result[3] 
result[4] <= add_sub_2qe:auto_generated.result[4] 
result[5] <= add_sub_2qe:auto_generated.result[5] 
result[6] <= add_sub_2qe:auto_generated.result[6] 
result[7] <= add_sub_2qe:auto_generated.result[7] 
result[8] <= add_sub_2qe:auto_generated.result[8] 
result[9] <= add_sub_2qe:auto_generated.result[9] 
result[10] <= add_sub_2qe:auto_generated.result[10] 
result[11] <= add_sub_2qe:auto_generated.result[11] 
result[12] <= add_sub_2qe:auto_generated.result[12] 
result[13] <= add_sub_2qe:auto_generated.result[13] 
result[14] <= add_sub_2qe:auto_generated.result[14] 
result[15] <= add_sub_2qe:auto_generated.result[15] 
result[16] <= add_sub_2qe:auto_generated.result[16] 
result[17] <= add_sub_2qe:auto_generated.result[17] 
result[18] <= add_sub_2qe:auto_generated.result[18] 
result[19] <= add_sub_2qe:auto_generated.result[19] 
result[20] <= add_sub_2qe:auto_generated.result[20] 
result[21] <= add_sub_2qe:auto_generated.result[21] 
result[22] <= add_sub_2qe:auto_generated.result[22] 
result[23] <= add_sub_2qe:auto_generated.result[23] 
result[24] <= add_sub_2qe:auto_generated.result[24] 
result[25] <= add_sub_2qe:auto_generated.result[25] 
result[26] <= add_sub_2qe:auto_generated.result[26] 
result[27] <= add_sub_2qe:auto_generated.result[27] 
result[28] <= add_sub_2qe:auto_generated.result[28] 
result[29] <= add_sub_2qe:auto_generated.result[29] 
result[30] <= add_sub_2qe:auto_generated.result[30] 
result[31] <= add_sub_2qe:auto_generated.result[31] 
cout <= <GND> 
overflow <= <GND> 
 
 
|top_level|SHA1_engine:inst|small_micro_32:inst4|Adder:Reg_add|lpm_add_sub:lpm_add_sub_component|add_sub_2qe:auto_generated 
dataa[0] => op_1.IN62 
dataa[1] => op_1.IN60 
dataa[2] => op_1.IN58 
dataa[3] => op_1.IN56 
dataa[4] => op_1.IN54 
dataa[5] => op_1.IN52 
dataa[6] => op_1.IN50 
dataa[7] => op_1.IN48 
dataa[8] => op_1.IN46 
dataa[9] => op_1.IN44 
dataa[10] => op_1.IN42 
dataa[11] => op_1.IN40 
dataa[12] => op_1.IN38 
dataa[13] => op_1.IN36 
dataa[14] => op_1.IN34 
dataa[15] => op_1.IN32 
dataa[16] => op_1.IN30 
dataa[17] => op_1.IN28 
dataa[18] => op_1.IN26 
dataa[19] => op_1.IN24 
dataa[20] => op_1.IN22 
dataa[21] => op_1.IN20 
dataa[22] => op_1.IN18 
dataa[23] => op_1.IN16 
dataa[24] => op_1.IN14 
dataa[25] => op_1.IN12 
dataa[26] => op_1.IN10 
dataa[27] => op_1.IN8 
dataa[28] => op_1.IN6 
dataa[29] => op_1.IN4 
dataa[30] => op_1.IN2 
dataa[31] => op_1.IN0 
datab[0] => op_1.IN63 
datab[1] => op_1.IN61 
datab[2] => op_1.IN59 
datab[3] => op_1.IN57 
datab[4] => op_1.IN55 
datab[5] => op_1.IN53 
datab[6] => op_1.IN51 
datab[7] => op_1.IN49 
datab[8] => op_1.IN47 
datab[9] => op_1.IN45 
datab[10] => op_1.IN43 
datab[11] => op_1.IN41 
datab[12] => op_1.IN39 
datab[13] => op_1.IN37 
datab[14] => op_1.IN35 
datab[15] => op_1.IN33 
datab[16] => op_1.IN31 
datab[17] => op_1.IN29 
datab[18] => op_1.IN27 
datab[19] => op_1.IN25 
datab[20] => op_1.IN23 
datab[21] => op_1.IN21 
datab[22] => op_1.IN19 
datab[23] => op_1.IN17 
datab[24] => op_1.IN15 
datab[25] => op_1.IN13 
datab[26] => op_1.IN11 
datab[27] => op_1.IN9 
datab[28] => op_1.IN7 
datab[29] => op_1.IN5 
datab[30] => op_1.IN3 
datab[31] => op_1.IN1 
result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[17] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[18] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[19] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[20] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[21] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[22] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[23] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[24] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[25] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[26] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[27] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[28] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[29] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[30] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
result[31] <= op_1.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|top_level|SHA1_engine:inst|One_Wire:inst 
resetn => r.Read_Byte_reg[0].ACLR 
resetn => r.Read_Byte_reg[1].ACLR 
resetn => r.Read_Byte_reg[2].ACLR 
resetn => r.Read_Byte_reg[3].ACLR 
resetn => r.Read_Byte_reg[4].ACLR 
resetn => r.Read_Byte_reg[5].ACLR 
resetn => r.Read_Byte_reg[6].ACLR 
resetn => r.Read_Byte_reg[7].ACLR 
resetn => r.Write_Byte_reg[0].ACLR 
resetn => r.Write_Byte_reg[1].ACLR 
resetn => r.Write_Byte_reg[2].ACLR 
resetn => r.Write_Byte_reg[3].ACLR 
resetn => r.Write_Byte_reg[4].ACLR 
resetn => r.Write_Byte_reg[5].ACLR 
resetn => r.Write_Byte_reg[6].ACLR 
resetn => r.Write_Byte_reg[7].ACLR 
resetn => r.B_Counter[0].ACLR 
resetn => r.B_Counter[1].ACLR 
resetn => r.B_Counter[2].ACLR 
resetn => r.T_Counter[0].ACLR 
resetn => r.T_Counter[1].ACLR 
resetn => r.T_Counter[2].ACLR 
resetn => r.T_Counter[3].ACLR 
resetn => r.T_Counter[4].ACLR 
resetn => r.T_Counter[5].ACLR 
resetn => r.T_Counter[6].ACLR 
resetn => r.T_Counter[7].ACLR 
resetn => r.T_Counter[8].ACLR 
resetn => r.T_Counter[9].ACLR 
resetn => r.T_Counter[10].ACLR 
resetn => r.T_Counter[11].ACLR 
resetn => r.T_Counter[12].ACLR 
resetn => r.T_Counter[13].ACLR 
resetn => r.Data_in_reg[0].ACLR 
resetn => r.Data_in_reg[1].ACLR 
resetn => r.Data_out_reg.ACLR 
resetn => r.One_Wire_State~3.DATAIN 
clock => r.Read_Byte_reg[0].CLK 
clock => r.Read_Byte_reg[1].CLK 
clock => r.Read_Byte_reg[2].CLK 
clock => r.Read_Byte_reg[3].CLK 
clock => r.Read_Byte_reg[4].CLK 
clock => r.Read_Byte_reg[5].CLK 
clock => r.Read_Byte_reg[6].CLK 
clock => r.Read_Byte_reg[7].CLK 
clock => r.Write_Byte_reg[0].CLK 
clock => r.Write_Byte_reg[1].CLK 
clock => r.Write_Byte_reg[2].CLK 
clock => r.Write_Byte_reg[3].CLK 
clock => r.Write_Byte_reg[4].CLK 
clock => r.Write_Byte_reg[5].CLK 
clock => r.Write_Byte_reg[6].CLK 
clock => r.Write_Byte_reg[7].CLK 
clock => r.B_Counter[0].CLK 
clock => r.B_Counter[1].CLK 
clock => r.B_Counter[2].CLK 
clock => r.T_Counter[0].CLK 
clock => r.T_Counter[1].CLK 
clock => r.T_Counter[2].CLK 
clock => r.T_Counter[3].CLK 
clock => r.T_Counter[4].CLK 
clock => r.T_Counter[5].CLK 
clock => r.T_Counter[6].CLK 
clock => r.T_Counter[7].CLK 
clock => r.T_Counter[8].CLK 
clock => r.T_Counter[9].CLK 
clock => r.T_Counter[10].CLK 
clock => r.T_Counter[11].CLK 
clock => r.T_Counter[12].CLK 
clock => r.T_Counter[13].CLK 
clock => r.Data_in_reg[0].CLK 
clock => r.Data_in_reg[1].CLK 
clock => r.Data_out_reg.CLK 
clock => r.One_Wire_State~1.DATAIN 
Address[0] => Mux0.IN10 
Address[0] => Mux1.IN10 
Address[0] => Mux2.IN10 
Address[0] => Mux3.IN10 
Address[0] => Mux4.IN10 
Address[1] => Mux0.IN9 
Address[1] => Mux1.IN9 
Address[1] => Mux2.IN9 
Address[1] => Mux3.IN9 
Address[1] => Mux4.IN9 
Address[2] => Mux0.IN8 
Address[2] => Mux1.IN8 
Address[2] => Mux2.IN8 
Address[2] => Mux3.IN8 
Address[2] => Mux4.IN8 
Address[3] => rin.OUTPUTSELECT 
Address[3] => rin.OUTPUTSELECT 
Address[3] => rin.OUTPUTSELECT 
Address[3] => rin.OUTPUTSELECT 
Address[3] => rin.OUTPUTSELECT 
Write_Byte_in[0] => r.Write_Byte_reg[0].DATAIN 
Write_Byte_in[1] => r.Write_Byte_reg[1].DATAIN 
Write_Byte_in[2] => r.Write_Byte_reg[2].DATAIN 
Write_Byte_in[3] => r.Write_Byte_reg[3].DATAIN 
Write_Byte_in[4] => r.Write_Byte_reg[4].DATAIN 
Write_Byte_in[5] => r.Write_Byte_reg[5].DATAIN 
Write_Byte_in[6] => r.Write_Byte_reg[6].DATAIN 
Write_Byte_in[7] => r.Write_Byte_reg[7].DATAIN 
Read_Byte_out[0] <= r.Read_Byte_reg[0].DB_MAX_OUTPUT_PORT_TYPE 
Read_Byte_out[1] <= r.Read_Byte_reg[1].DB_MAX_OUTPUT_PORT_TYPE 
Read_Byte_out[2] <= r.Read_Byte_reg[2].DB_MAX_OUTPUT_PORT_TYPE 
Read_Byte_out[3] <= r.Read_Byte_reg[3].DB_MAX_OUTPUT_PORT_TYPE 
Read_Byte_out[4] <= r.Read_Byte_reg[4].DB_MAX_OUTPUT_PORT_TYPE 
Read_Byte_out[5] <= r.Read_Byte_reg[5].DB_MAX_OUTPUT_PORT_TYPE 
Read_Byte_out[6] <= r.Read_Byte_reg[6].DB_MAX_OUTPUT_PORT_TYPE 
Read_Byte_out[7] <= r.Read_Byte_reg[7].DB_MAX_OUTPUT_PORT_TYPE 
One_Wire_data <> One_Wire_data 
Busy <= Busy.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|top_level|SHA1_engine:inst|RNG_8Bits:inst2 
clock => r.Shift_reg[0].CLK 
clock => r.Shift_reg[1].CLK 
clock => r.Shift_reg[2].CLK 
clock => r.Shift_reg[3].CLK 
clock => r.Shift_reg[4].CLK 
clock => r.Shift_reg[5].CLK 
clock => r.Shift_reg[6].CLK 
clock => r.Shift_reg[7].CLK 
clock => r.MetaStable_reg[0].CLK 
clock => r.MetaStable_reg[1].CLK 
reset => r.Shift_reg[0].ACLR 
reset => r.Shift_reg[1].ACLR 
reset => r.Shift_reg[2].ACLR 
reset => r.Shift_reg[3].ACLR 
reset => r.Shift_reg[4].ACLR 
reset => r.Shift_reg[5].ACLR 
reset => r.Shift_reg[6].ACLR 
reset => r.Shift_reg[7].ACLR 
reset => r.MetaStable_reg[0].ACLR 
reset => r.MetaStable_reg[1].ACLR 
RNG_Byte[0] <= r.Shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE 
RNG_Byte[1] <= r.Shift_reg[1].DB_MAX_OUTPUT_PORT_TYPE 
RNG_Byte[2] <= r.Shift_reg[2].DB_MAX_OUTPUT_PORT_TYPE 
RNG_Byte[3] <= r.Shift_reg[3].DB_MAX_OUTPUT_PORT_TYPE 
RNG_Byte[4] <= r.Shift_reg[4].DB_MAX_OUTPUT_PORT_TYPE 
RNG_Byte[5] <= r.Shift_reg[5].DB_MAX_OUTPUT_PORT_TYPE 
RNG_Byte[6] <= r.Shift_reg[6].DB_MAX_OUTPUT_PORT_TYPE 
RNG_Byte[7] <= r.Shift_reg[7].DB_MAX_OUTPUT_PORT_TYPE 
 
 
|top_level|count:inst3 
clk_en => lpm_counter:lpm_counter_component.clk_en 
clock => lpm_counter:lpm_counter_component.clock 
q[0] <= lpm_counter:lpm_counter_component.q[0] 
q[1] <= lpm_counter:lpm_counter_component.q[1] 
q[2] <= lpm_counter:lpm_counter_component.q[2] 
q[3] <= lpm_counter:lpm_counter_component.q[3] 
q[4] <= lpm_counter:lpm_counter_component.q[4] 
q[5] <= lpm_counter:lpm_counter_component.q[5] 
q[6] <= lpm_counter:lpm_counter_component.q[6] 
q[7] <= lpm_counter:lpm_counter_component.q[7] 
 
 
|top_level|count:inst3|lpm_counter:lpm_counter_component 
clock => cntr_aai:auto_generated.clock 
clk_en => cntr_aai:auto_generated.clk_en 
cnt_en => ~NO_FANOUT~ 
updown => ~NO_FANOUT~ 
aclr => ~NO_FANOUT~ 
aset => ~NO_FANOUT~ 
aconst => ~NO_FANOUT~ 
aload => ~NO_FANOUT~ 
sclr => ~NO_FANOUT~ 
sset => ~NO_FANOUT~ 
sconst => ~NO_FANOUT~ 
sload => ~NO_FANOUT~ 
data[0] => ~NO_FANOUT~ 
data[1] => ~NO_FANOUT~ 
data[2] => ~NO_FANOUT~ 
data[3] => ~NO_FANOUT~ 
data[4] => ~NO_FANOUT~ 
data[5] => ~NO_FANOUT~ 
data[6] => ~NO_FANOUT~ 
data[7] => ~NO_FANOUT~ 
cin => ~NO_FANOUT~ 
q[0] <= cntr_aai:auto_generated.q[0] 
q[1] <= cntr_aai:auto_generated.q[1] 
q[2] <= cntr_aai:auto_generated.q[2] 
q[3] <= cntr_aai:auto_generated.q[3] 
q[4] <= cntr_aai:auto_generated.q[4] 
q[5] <= cntr_aai:auto_generated.q[5] 
q[6] <= cntr_aai:auto_generated.q[6] 
q[7] <= cntr_aai:auto_generated.q[7] 
cout <= <GND> 
eq[0] <= <GND> 
eq[1] <= <GND> 
eq[2] <= <GND> 
eq[3] <= <GND> 
eq[4] <= <GND> 
eq[5] <= <GND> 
eq[6] <= <GND> 
eq[7] <= <GND> 
eq[8] <= <GND> 
eq[9] <= <GND> 
eq[10] <= <GND> 
eq[11] <= <GND> 
eq[12] <= <GND> 
eq[13] <= <GND> 
eq[14] <= <GND> 
eq[15] <= <GND> 
 
 
|top_level|count:inst3|lpm_counter:lpm_counter_component|cntr_aai:auto_generated 
clk_en => counter_reg_bit1a[7].IN0 
clock => counter_reg_bit1a[7].CLK 
clock => counter_reg_bit1a[6].CLK 
clock => counter_reg_bit1a[5].CLK 
clock => counter_reg_bit1a[4].CLK 
clock => counter_reg_bit1a[3].CLK 
clock => counter_reg_bit1a[2].CLK 
clock => counter_reg_bit1a[1].CLK 
clock => counter_reg_bit1a[0].CLK 
q[0] <= counter_reg_bit1a[0].REGOUT 
q[1] <= counter_reg_bit1a[1].REGOUT 
q[2] <= counter_reg_bit1a[2].REGOUT 
q[3] <= counter_reg_bit1a[3].REGOUT 
q[4] <= counter_reg_bit1a[4].REGOUT 
q[5] <= counter_reg_bit1a[5].REGOUT 
q[6] <= counter_reg_bit1a[6].REGOUT 
q[7] <= counter_reg_bit1a[7].REGOUT