www.pudn.com > DS28E01_final.zip > mux_njb.tdf, change:2014-07-31,size:5577b


--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II" LPM_SIZE=4 LPM_WIDTH=9 LPM_WIDTHS=2 data result sel 
--VERSION_BEGIN 9.1 cbx_lpm_mux 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2009 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
 
--synthesis_resources = lut 9  
SUBDESIGN mux_njb 
(  
	data[35..0]	:	input; 
	result[8..0]	:	output; 
	sel[1..0]	:	input; 
)  
VARIABLE 
	l1_w0_n0_mux_dataout	:	WIRE; 
	l1_w0_n1_mux_dataout	:	WIRE; 
	l1_w1_n0_mux_dataout	:	WIRE; 
	l1_w1_n1_mux_dataout	:	WIRE; 
	l1_w2_n0_mux_dataout	:	WIRE; 
	l1_w2_n1_mux_dataout	:	WIRE; 
	l1_w3_n0_mux_dataout	:	WIRE; 
	l1_w3_n1_mux_dataout	:	WIRE; 
	l1_w4_n0_mux_dataout	:	WIRE; 
	l1_w4_n1_mux_dataout	:	WIRE; 
	l1_w5_n0_mux_dataout	:	WIRE; 
	l1_w5_n1_mux_dataout	:	WIRE; 
	l1_w6_n0_mux_dataout	:	WIRE; 
	l1_w6_n1_mux_dataout	:	WIRE; 
	l1_w7_n0_mux_dataout	:	WIRE; 
	l1_w7_n1_mux_dataout	:	WIRE; 
	l1_w8_n0_mux_dataout	:	WIRE; 
	l1_w8_n1_mux_dataout	:	WIRE; 
	l2_w0_n0_mux_dataout	:	WIRE; 
	l2_w1_n0_mux_dataout	:	WIRE; 
	l2_w2_n0_mux_dataout	:	WIRE; 
	l2_w3_n0_mux_dataout	:	WIRE; 
	l2_w4_n0_mux_dataout	:	WIRE; 
	l2_w5_n0_mux_dataout	:	WIRE; 
	l2_w6_n0_mux_dataout	:	WIRE; 
	l2_w7_n0_mux_dataout	:	WIRE; 
	l2_w8_n0_mux_dataout	:	WIRE; 
	data_wire[53..0]	: WIRE; 
	result_wire_ext[8..0]	: WIRE; 
	sel_wire[3..0]	: WIRE; 
 
BEGIN  
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[0..0]; 
	l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[18..18]; 
	l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[1..1]; 
	l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[19..19]; 
	l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[2..2]; 
	l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[20..20]; 
	l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[3..3]; 
	l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[21..21]; 
	l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[4..4]; 
	l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[22..22]; 
	l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[5..5]; 
	l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[32..32] # !(sel_wire[0..0]) & data_wire[23..23]; 
	l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[6..6]; 
	l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[33..33] # !(sel_wire[0..0]) & data_wire[24..24]; 
	l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[16..16] # !(sel_wire[0..0]) & data_wire[7..7]; 
	l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[34..34] # !(sel_wire[0..0]) & data_wire[25..25]; 
	l1_w8_n0_mux_dataout = sel_wire[0..0] & data_wire[17..17] # !(sel_wire[0..0]) & data_wire[8..8]; 
	l1_w8_n1_mux_dataout = sel_wire[0..0] & data_wire[35..35] # !(sel_wire[0..0]) & data_wire[26..26]; 
	l2_w0_n0_mux_dataout = sel_wire[3..3] & data_wire[37..37] # !(sel_wire[3..3]) & data_wire[36..36]; 
	l2_w1_n0_mux_dataout = sel_wire[3..3] & data_wire[39..39] # !(sel_wire[3..3]) & data_wire[38..38]; 
	l2_w2_n0_mux_dataout = sel_wire[3..3] & data_wire[41..41] # !(sel_wire[3..3]) & data_wire[40..40]; 
	l2_w3_n0_mux_dataout = sel_wire[3..3] & data_wire[43..43] # !(sel_wire[3..3]) & data_wire[42..42]; 
	l2_w4_n0_mux_dataout = sel_wire[3..3] & data_wire[45..45] # !(sel_wire[3..3]) & data_wire[44..44]; 
	l2_w5_n0_mux_dataout = sel_wire[3..3] & data_wire[47..47] # !(sel_wire[3..3]) & data_wire[46..46]; 
	l2_w6_n0_mux_dataout = sel_wire[3..3] & data_wire[49..49] # !(sel_wire[3..3]) & data_wire[48..48]; 
	l2_w7_n0_mux_dataout = sel_wire[3..3] & data_wire[51..51] # !(sel_wire[3..3]) & data_wire[50..50]; 
	l2_w8_n0_mux_dataout = sel_wire[3..3] & data_wire[53..53] # !(sel_wire[3..3]) & data_wire[52..52]; 
	data_wire[] = ( l1_w8_n1_mux_dataout, l1_w8_n0_mux_dataout, l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]); 
	result[] = result_wire_ext[]; 
	result_wire_ext[] = ( l2_w8_n0_mux_dataout, l2_w7_n0_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n0_mux_dataout); 
	sel_wire[] = ( sel[1..1], B"00", sel[0..0]); 
END; 
--VALID FILE