www.pudn.com > DS28E01_final.zip > mux_5lb.tdf, change:2014-07-31,size:34945b


--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II" LPM_SIZE=4 LPM_WIDTH=70 LPM_WIDTHS=2 data result sel 
--VERSION_BEGIN 9.1 cbx_lpm_mux 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2009 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
 
--synthesis_resources = lut 70  
SUBDESIGN mux_5lb 
(  
	data[279..0]	:	input; 
	result[69..0]	:	output; 
	sel[1..0]	:	input; 
)  
VARIABLE 
	l1_w0_n0_mux_dataout	:	WIRE; 
	l1_w0_n1_mux_dataout	:	WIRE; 
	l1_w10_n0_mux_dataout	:	WIRE; 
	l1_w10_n1_mux_dataout	:	WIRE; 
	l1_w11_n0_mux_dataout	:	WIRE; 
	l1_w11_n1_mux_dataout	:	WIRE; 
	l1_w12_n0_mux_dataout	:	WIRE; 
	l1_w12_n1_mux_dataout	:	WIRE; 
	l1_w13_n0_mux_dataout	:	WIRE; 
	l1_w13_n1_mux_dataout	:	WIRE; 
	l1_w14_n0_mux_dataout	:	WIRE; 
	l1_w14_n1_mux_dataout	:	WIRE; 
	l1_w15_n0_mux_dataout	:	WIRE; 
	l1_w15_n1_mux_dataout	:	WIRE; 
	l1_w16_n0_mux_dataout	:	WIRE; 
	l1_w16_n1_mux_dataout	:	WIRE; 
	l1_w17_n0_mux_dataout	:	WIRE; 
	l1_w17_n1_mux_dataout	:	WIRE; 
	l1_w18_n0_mux_dataout	:	WIRE; 
	l1_w18_n1_mux_dataout	:	WIRE; 
	l1_w19_n0_mux_dataout	:	WIRE; 
	l1_w19_n1_mux_dataout	:	WIRE; 
	l1_w1_n0_mux_dataout	:	WIRE; 
	l1_w1_n1_mux_dataout	:	WIRE; 
	l1_w20_n0_mux_dataout	:	WIRE; 
	l1_w20_n1_mux_dataout	:	WIRE; 
	l1_w21_n0_mux_dataout	:	WIRE; 
	l1_w21_n1_mux_dataout	:	WIRE; 
	l1_w22_n0_mux_dataout	:	WIRE; 
	l1_w22_n1_mux_dataout	:	WIRE; 
	l1_w23_n0_mux_dataout	:	WIRE; 
	l1_w23_n1_mux_dataout	:	WIRE; 
	l1_w24_n0_mux_dataout	:	WIRE; 
	l1_w24_n1_mux_dataout	:	WIRE; 
	l1_w25_n0_mux_dataout	:	WIRE; 
	l1_w25_n1_mux_dataout	:	WIRE; 
	l1_w26_n0_mux_dataout	:	WIRE; 
	l1_w26_n1_mux_dataout	:	WIRE; 
	l1_w27_n0_mux_dataout	:	WIRE; 
	l1_w27_n1_mux_dataout	:	WIRE; 
	l1_w28_n0_mux_dataout	:	WIRE; 
	l1_w28_n1_mux_dataout	:	WIRE; 
	l1_w29_n0_mux_dataout	:	WIRE; 
	l1_w29_n1_mux_dataout	:	WIRE; 
	l1_w2_n0_mux_dataout	:	WIRE; 
	l1_w2_n1_mux_dataout	:	WIRE; 
	l1_w30_n0_mux_dataout	:	WIRE; 
	l1_w30_n1_mux_dataout	:	WIRE; 
	l1_w31_n0_mux_dataout	:	WIRE; 
	l1_w31_n1_mux_dataout	:	WIRE; 
	l1_w32_n0_mux_dataout	:	WIRE; 
	l1_w32_n1_mux_dataout	:	WIRE; 
	l1_w33_n0_mux_dataout	:	WIRE; 
	l1_w33_n1_mux_dataout	:	WIRE; 
	l1_w34_n0_mux_dataout	:	WIRE; 
	l1_w34_n1_mux_dataout	:	WIRE; 
	l1_w35_n0_mux_dataout	:	WIRE; 
	l1_w35_n1_mux_dataout	:	WIRE; 
	l1_w36_n0_mux_dataout	:	WIRE; 
	l1_w36_n1_mux_dataout	:	WIRE; 
	l1_w37_n0_mux_dataout	:	WIRE; 
	l1_w37_n1_mux_dataout	:	WIRE; 
	l1_w38_n0_mux_dataout	:	WIRE; 
	l1_w38_n1_mux_dataout	:	WIRE; 
	l1_w39_n0_mux_dataout	:	WIRE; 
	l1_w39_n1_mux_dataout	:	WIRE; 
	l1_w3_n0_mux_dataout	:	WIRE; 
	l1_w3_n1_mux_dataout	:	WIRE; 
	l1_w40_n0_mux_dataout	:	WIRE; 
	l1_w40_n1_mux_dataout	:	WIRE; 
	l1_w41_n0_mux_dataout	:	WIRE; 
	l1_w41_n1_mux_dataout	:	WIRE; 
	l1_w42_n0_mux_dataout	:	WIRE; 
	l1_w42_n1_mux_dataout	:	WIRE; 
	l1_w43_n0_mux_dataout	:	WIRE; 
	l1_w43_n1_mux_dataout	:	WIRE; 
	l1_w44_n0_mux_dataout	:	WIRE; 
	l1_w44_n1_mux_dataout	:	WIRE; 
	l1_w45_n0_mux_dataout	:	WIRE; 
	l1_w45_n1_mux_dataout	:	WIRE; 
	l1_w46_n0_mux_dataout	:	WIRE; 
	l1_w46_n1_mux_dataout	:	WIRE; 
	l1_w47_n0_mux_dataout	:	WIRE; 
	l1_w47_n1_mux_dataout	:	WIRE; 
	l1_w48_n0_mux_dataout	:	WIRE; 
	l1_w48_n1_mux_dataout	:	WIRE; 
	l1_w49_n0_mux_dataout	:	WIRE; 
	l1_w49_n1_mux_dataout	:	WIRE; 
	l1_w4_n0_mux_dataout	:	WIRE; 
	l1_w4_n1_mux_dataout	:	WIRE; 
	l1_w50_n0_mux_dataout	:	WIRE; 
	l1_w50_n1_mux_dataout	:	WIRE; 
	l1_w51_n0_mux_dataout	:	WIRE; 
	l1_w51_n1_mux_dataout	:	WIRE; 
	l1_w52_n0_mux_dataout	:	WIRE; 
	l1_w52_n1_mux_dataout	:	WIRE; 
	l1_w53_n0_mux_dataout	:	WIRE; 
	l1_w53_n1_mux_dataout	:	WIRE; 
	l1_w54_n0_mux_dataout	:	WIRE; 
	l1_w54_n1_mux_dataout	:	WIRE; 
	l1_w55_n0_mux_dataout	:	WIRE; 
	l1_w55_n1_mux_dataout	:	WIRE; 
	l1_w56_n0_mux_dataout	:	WIRE; 
	l1_w56_n1_mux_dataout	:	WIRE; 
	l1_w57_n0_mux_dataout	:	WIRE; 
	l1_w57_n1_mux_dataout	:	WIRE; 
	l1_w58_n0_mux_dataout	:	WIRE; 
	l1_w58_n1_mux_dataout	:	WIRE; 
	l1_w59_n0_mux_dataout	:	WIRE; 
	l1_w59_n1_mux_dataout	:	WIRE; 
	l1_w5_n0_mux_dataout	:	WIRE; 
	l1_w5_n1_mux_dataout	:	WIRE; 
	l1_w60_n0_mux_dataout	:	WIRE; 
	l1_w60_n1_mux_dataout	:	WIRE; 
	l1_w61_n0_mux_dataout	:	WIRE; 
	l1_w61_n1_mux_dataout	:	WIRE; 
	l1_w62_n0_mux_dataout	:	WIRE; 
	l1_w62_n1_mux_dataout	:	WIRE; 
	l1_w63_n0_mux_dataout	:	WIRE; 
	l1_w63_n1_mux_dataout	:	WIRE; 
	l1_w64_n0_mux_dataout	:	WIRE; 
	l1_w64_n1_mux_dataout	:	WIRE; 
	l1_w65_n0_mux_dataout	:	WIRE; 
	l1_w65_n1_mux_dataout	:	WIRE; 
	l1_w66_n0_mux_dataout	:	WIRE; 
	l1_w66_n1_mux_dataout	:	WIRE; 
	l1_w67_n0_mux_dataout	:	WIRE; 
	l1_w67_n1_mux_dataout	:	WIRE; 
	l1_w68_n0_mux_dataout	:	WIRE; 
	l1_w68_n1_mux_dataout	:	WIRE; 
	l1_w69_n0_mux_dataout	:	WIRE; 
	l1_w69_n1_mux_dataout	:	WIRE; 
	l1_w6_n0_mux_dataout	:	WIRE; 
	l1_w6_n1_mux_dataout	:	WIRE; 
	l1_w7_n0_mux_dataout	:	WIRE; 
	l1_w7_n1_mux_dataout	:	WIRE; 
	l1_w8_n0_mux_dataout	:	WIRE; 
	l1_w8_n1_mux_dataout	:	WIRE; 
	l1_w9_n0_mux_dataout	:	WIRE; 
	l1_w9_n1_mux_dataout	:	WIRE; 
	l2_w0_n0_mux_dataout	:	WIRE; 
	l2_w10_n0_mux_dataout	:	WIRE; 
	l2_w11_n0_mux_dataout	:	WIRE; 
	l2_w12_n0_mux_dataout	:	WIRE; 
	l2_w13_n0_mux_dataout	:	WIRE; 
	l2_w14_n0_mux_dataout	:	WIRE; 
	l2_w15_n0_mux_dataout	:	WIRE; 
	l2_w16_n0_mux_dataout	:	WIRE; 
	l2_w17_n0_mux_dataout	:	WIRE; 
	l2_w18_n0_mux_dataout	:	WIRE; 
	l2_w19_n0_mux_dataout	:	WIRE; 
	l2_w1_n0_mux_dataout	:	WIRE; 
	l2_w20_n0_mux_dataout	:	WIRE; 
	l2_w21_n0_mux_dataout	:	WIRE; 
	l2_w22_n0_mux_dataout	:	WIRE; 
	l2_w23_n0_mux_dataout	:	WIRE; 
	l2_w24_n0_mux_dataout	:	WIRE; 
	l2_w25_n0_mux_dataout	:	WIRE; 
	l2_w26_n0_mux_dataout	:	WIRE; 
	l2_w27_n0_mux_dataout	:	WIRE; 
	l2_w28_n0_mux_dataout	:	WIRE; 
	l2_w29_n0_mux_dataout	:	WIRE; 
	l2_w2_n0_mux_dataout	:	WIRE; 
	l2_w30_n0_mux_dataout	:	WIRE; 
	l2_w31_n0_mux_dataout	:	WIRE; 
	l2_w32_n0_mux_dataout	:	WIRE; 
	l2_w33_n0_mux_dataout	:	WIRE; 
	l2_w34_n0_mux_dataout	:	WIRE; 
	l2_w35_n0_mux_dataout	:	WIRE; 
	l2_w36_n0_mux_dataout	:	WIRE; 
	l2_w37_n0_mux_dataout	:	WIRE; 
	l2_w38_n0_mux_dataout	:	WIRE; 
	l2_w39_n0_mux_dataout	:	WIRE; 
	l2_w3_n0_mux_dataout	:	WIRE; 
	l2_w40_n0_mux_dataout	:	WIRE; 
	l2_w41_n0_mux_dataout	:	WIRE; 
	l2_w42_n0_mux_dataout	:	WIRE; 
	l2_w43_n0_mux_dataout	:	WIRE; 
	l2_w44_n0_mux_dataout	:	WIRE; 
	l2_w45_n0_mux_dataout	:	WIRE; 
	l2_w46_n0_mux_dataout	:	WIRE; 
	l2_w47_n0_mux_dataout	:	WIRE; 
	l2_w48_n0_mux_dataout	:	WIRE; 
	l2_w49_n0_mux_dataout	:	WIRE; 
	l2_w4_n0_mux_dataout	:	WIRE; 
	l2_w50_n0_mux_dataout	:	WIRE; 
	l2_w51_n0_mux_dataout	:	WIRE; 
	l2_w52_n0_mux_dataout	:	WIRE; 
	l2_w53_n0_mux_dataout	:	WIRE; 
	l2_w54_n0_mux_dataout	:	WIRE; 
	l2_w55_n0_mux_dataout	:	WIRE; 
	l2_w56_n0_mux_dataout	:	WIRE; 
	l2_w57_n0_mux_dataout	:	WIRE; 
	l2_w58_n0_mux_dataout	:	WIRE; 
	l2_w59_n0_mux_dataout	:	WIRE; 
	l2_w5_n0_mux_dataout	:	WIRE; 
	l2_w60_n0_mux_dataout	:	WIRE; 
	l2_w61_n0_mux_dataout	:	WIRE; 
	l2_w62_n0_mux_dataout	:	WIRE; 
	l2_w63_n0_mux_dataout	:	WIRE; 
	l2_w64_n0_mux_dataout	:	WIRE; 
	l2_w65_n0_mux_dataout	:	WIRE; 
	l2_w66_n0_mux_dataout	:	WIRE; 
	l2_w67_n0_mux_dataout	:	WIRE; 
	l2_w68_n0_mux_dataout	:	WIRE; 
	l2_w69_n0_mux_dataout	:	WIRE; 
	l2_w6_n0_mux_dataout	:	WIRE; 
	l2_w7_n0_mux_dataout	:	WIRE; 
	l2_w8_n0_mux_dataout	:	WIRE; 
	l2_w9_n0_mux_dataout	:	WIRE; 
	data_wire[419..0]	: WIRE; 
	result_wire_ext[69..0]	: WIRE; 
	sel_wire[3..0]	: WIRE; 
 
BEGIN  
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[70..70] # !(sel_wire[0..0]) & data_wire[0..0]; 
	l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[210..210] # !(sel_wire[0..0]) & data_wire[140..140]; 
	l1_w10_n0_mux_dataout = sel_wire[0..0] & data_wire[80..80] # !(sel_wire[0..0]) & data_wire[10..10]; 
	l1_w10_n1_mux_dataout = sel_wire[0..0] & data_wire[220..220] # !(sel_wire[0..0]) & data_wire[150..150]; 
	l1_w11_n0_mux_dataout = sel_wire[0..0] & data_wire[81..81] # !(sel_wire[0..0]) & data_wire[11..11]; 
	l1_w11_n1_mux_dataout = sel_wire[0..0] & data_wire[221..221] # !(sel_wire[0..0]) & data_wire[151..151]; 
	l1_w12_n0_mux_dataout = sel_wire[0..0] & data_wire[82..82] # !(sel_wire[0..0]) & data_wire[12..12]; 
	l1_w12_n1_mux_dataout = sel_wire[0..0] & data_wire[222..222] # !(sel_wire[0..0]) & data_wire[152..152]; 
	l1_w13_n0_mux_dataout = sel_wire[0..0] & data_wire[83..83] # !(sel_wire[0..0]) & data_wire[13..13]; 
	l1_w13_n1_mux_dataout = sel_wire[0..0] & data_wire[223..223] # !(sel_wire[0..0]) & data_wire[153..153]; 
	l1_w14_n0_mux_dataout = sel_wire[0..0] & data_wire[84..84] # !(sel_wire[0..0]) & data_wire[14..14]; 
	l1_w14_n1_mux_dataout = sel_wire[0..0] & data_wire[224..224] # !(sel_wire[0..0]) & data_wire[154..154]; 
	l1_w15_n0_mux_dataout = sel_wire[0..0] & data_wire[85..85] # !(sel_wire[0..0]) & data_wire[15..15]; 
	l1_w15_n1_mux_dataout = sel_wire[0..0] & data_wire[225..225] # !(sel_wire[0..0]) & data_wire[155..155]; 
	l1_w16_n0_mux_dataout = sel_wire[0..0] & data_wire[86..86] # !(sel_wire[0..0]) & data_wire[16..16]; 
	l1_w16_n1_mux_dataout = sel_wire[0..0] & data_wire[226..226] # !(sel_wire[0..0]) & data_wire[156..156]; 
	l1_w17_n0_mux_dataout = sel_wire[0..0] & data_wire[87..87] # !(sel_wire[0..0]) & data_wire[17..17]; 
	l1_w17_n1_mux_dataout = sel_wire[0..0] & data_wire[227..227] # !(sel_wire[0..0]) & data_wire[157..157]; 
	l1_w18_n0_mux_dataout = sel_wire[0..0] & data_wire[88..88] # !(sel_wire[0..0]) & data_wire[18..18]; 
	l1_w18_n1_mux_dataout = sel_wire[0..0] & data_wire[228..228] # !(sel_wire[0..0]) & data_wire[158..158]; 
	l1_w19_n0_mux_dataout = sel_wire[0..0] & data_wire[89..89] # !(sel_wire[0..0]) & data_wire[19..19]; 
	l1_w19_n1_mux_dataout = sel_wire[0..0] & data_wire[229..229] # !(sel_wire[0..0]) & data_wire[159..159]; 
	l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[71..71] # !(sel_wire[0..0]) & data_wire[1..1]; 
	l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[211..211] # !(sel_wire[0..0]) & data_wire[141..141]; 
	l1_w20_n0_mux_dataout = sel_wire[0..0] & data_wire[90..90] # !(sel_wire[0..0]) & data_wire[20..20]; 
	l1_w20_n1_mux_dataout = sel_wire[0..0] & data_wire[230..230] # !(sel_wire[0..0]) & data_wire[160..160]; 
	l1_w21_n0_mux_dataout = sel_wire[0..0] & data_wire[91..91] # !(sel_wire[0..0]) & data_wire[21..21]; 
	l1_w21_n1_mux_dataout = sel_wire[0..0] & data_wire[231..231] # !(sel_wire[0..0]) & data_wire[161..161]; 
	l1_w22_n0_mux_dataout = sel_wire[0..0] & data_wire[92..92] # !(sel_wire[0..0]) & data_wire[22..22]; 
	l1_w22_n1_mux_dataout = sel_wire[0..0] & data_wire[232..232] # !(sel_wire[0..0]) & data_wire[162..162]; 
	l1_w23_n0_mux_dataout = sel_wire[0..0] & data_wire[93..93] # !(sel_wire[0..0]) & data_wire[23..23]; 
	l1_w23_n1_mux_dataout = sel_wire[0..0] & data_wire[233..233] # !(sel_wire[0..0]) & data_wire[163..163]; 
	l1_w24_n0_mux_dataout = sel_wire[0..0] & data_wire[94..94] # !(sel_wire[0..0]) & data_wire[24..24]; 
	l1_w24_n1_mux_dataout = sel_wire[0..0] & data_wire[234..234] # !(sel_wire[0..0]) & data_wire[164..164]; 
	l1_w25_n0_mux_dataout = sel_wire[0..0] & data_wire[95..95] # !(sel_wire[0..0]) & data_wire[25..25]; 
	l1_w25_n1_mux_dataout = sel_wire[0..0] & data_wire[235..235] # !(sel_wire[0..0]) & data_wire[165..165]; 
	l1_w26_n0_mux_dataout = sel_wire[0..0] & data_wire[96..96] # !(sel_wire[0..0]) & data_wire[26..26]; 
	l1_w26_n1_mux_dataout = sel_wire[0..0] & data_wire[236..236] # !(sel_wire[0..0]) & data_wire[166..166]; 
	l1_w27_n0_mux_dataout = sel_wire[0..0] & data_wire[97..97] # !(sel_wire[0..0]) & data_wire[27..27]; 
	l1_w27_n1_mux_dataout = sel_wire[0..0] & data_wire[237..237] # !(sel_wire[0..0]) & data_wire[167..167]; 
	l1_w28_n0_mux_dataout = sel_wire[0..0] & data_wire[98..98] # !(sel_wire[0..0]) & data_wire[28..28]; 
	l1_w28_n1_mux_dataout = sel_wire[0..0] & data_wire[238..238] # !(sel_wire[0..0]) & data_wire[168..168]; 
	l1_w29_n0_mux_dataout = sel_wire[0..0] & data_wire[99..99] # !(sel_wire[0..0]) & data_wire[29..29]; 
	l1_w29_n1_mux_dataout = sel_wire[0..0] & data_wire[239..239] # !(sel_wire[0..0]) & data_wire[169..169]; 
	l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[72..72] # !(sel_wire[0..0]) & data_wire[2..2]; 
	l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[212..212] # !(sel_wire[0..0]) & data_wire[142..142]; 
	l1_w30_n0_mux_dataout = sel_wire[0..0] & data_wire[100..100] # !(sel_wire[0..0]) & data_wire[30..30]; 
	l1_w30_n1_mux_dataout = sel_wire[0..0] & data_wire[240..240] # !(sel_wire[0..0]) & data_wire[170..170]; 
	l1_w31_n0_mux_dataout = sel_wire[0..0] & data_wire[101..101] # !(sel_wire[0..0]) & data_wire[31..31]; 
	l1_w31_n1_mux_dataout = sel_wire[0..0] & data_wire[241..241] # !(sel_wire[0..0]) & data_wire[171..171]; 
	l1_w32_n0_mux_dataout = sel_wire[0..0] & data_wire[102..102] # !(sel_wire[0..0]) & data_wire[32..32]; 
	l1_w32_n1_mux_dataout = sel_wire[0..0] & data_wire[242..242] # !(sel_wire[0..0]) & data_wire[172..172]; 
	l1_w33_n0_mux_dataout = sel_wire[0..0] & data_wire[103..103] # !(sel_wire[0..0]) & data_wire[33..33]; 
	l1_w33_n1_mux_dataout = sel_wire[0..0] & data_wire[243..243] # !(sel_wire[0..0]) & data_wire[173..173]; 
	l1_w34_n0_mux_dataout = sel_wire[0..0] & data_wire[104..104] # !(sel_wire[0..0]) & data_wire[34..34]; 
	l1_w34_n1_mux_dataout = sel_wire[0..0] & data_wire[244..244] # !(sel_wire[0..0]) & data_wire[174..174]; 
	l1_w35_n0_mux_dataout = sel_wire[0..0] & data_wire[105..105] # !(sel_wire[0..0]) & data_wire[35..35]; 
	l1_w35_n1_mux_dataout = sel_wire[0..0] & data_wire[245..245] # !(sel_wire[0..0]) & data_wire[175..175]; 
	l1_w36_n0_mux_dataout = sel_wire[0..0] & data_wire[106..106] # !(sel_wire[0..0]) & data_wire[36..36]; 
	l1_w36_n1_mux_dataout = sel_wire[0..0] & data_wire[246..246] # !(sel_wire[0..0]) & data_wire[176..176]; 
	l1_w37_n0_mux_dataout = sel_wire[0..0] & data_wire[107..107] # !(sel_wire[0..0]) & data_wire[37..37]; 
	l1_w37_n1_mux_dataout = sel_wire[0..0] & data_wire[247..247] # !(sel_wire[0..0]) & data_wire[177..177]; 
	l1_w38_n0_mux_dataout = sel_wire[0..0] & data_wire[108..108] # !(sel_wire[0..0]) & data_wire[38..38]; 
	l1_w38_n1_mux_dataout = sel_wire[0..0] & data_wire[248..248] # !(sel_wire[0..0]) & data_wire[178..178]; 
	l1_w39_n0_mux_dataout = sel_wire[0..0] & data_wire[109..109] # !(sel_wire[0..0]) & data_wire[39..39]; 
	l1_w39_n1_mux_dataout = sel_wire[0..0] & data_wire[249..249] # !(sel_wire[0..0]) & data_wire[179..179]; 
	l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[73..73] # !(sel_wire[0..0]) & data_wire[3..3]; 
	l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[213..213] # !(sel_wire[0..0]) & data_wire[143..143]; 
	l1_w40_n0_mux_dataout = sel_wire[0..0] & data_wire[110..110] # !(sel_wire[0..0]) & data_wire[40..40]; 
	l1_w40_n1_mux_dataout = sel_wire[0..0] & data_wire[250..250] # !(sel_wire[0..0]) & data_wire[180..180]; 
	l1_w41_n0_mux_dataout = sel_wire[0..0] & data_wire[111..111] # !(sel_wire[0..0]) & data_wire[41..41]; 
	l1_w41_n1_mux_dataout = sel_wire[0..0] & data_wire[251..251] # !(sel_wire[0..0]) & data_wire[181..181]; 
	l1_w42_n0_mux_dataout = sel_wire[0..0] & data_wire[112..112] # !(sel_wire[0..0]) & data_wire[42..42]; 
	l1_w42_n1_mux_dataout = sel_wire[0..0] & data_wire[252..252] # !(sel_wire[0..0]) & data_wire[182..182]; 
	l1_w43_n0_mux_dataout = sel_wire[0..0] & data_wire[113..113] # !(sel_wire[0..0]) & data_wire[43..43]; 
	l1_w43_n1_mux_dataout = sel_wire[0..0] & data_wire[253..253] # !(sel_wire[0..0]) & data_wire[183..183]; 
	l1_w44_n0_mux_dataout = sel_wire[0..0] & data_wire[114..114] # !(sel_wire[0..0]) & data_wire[44..44]; 
	l1_w44_n1_mux_dataout = sel_wire[0..0] & data_wire[254..254] # !(sel_wire[0..0]) & data_wire[184..184]; 
	l1_w45_n0_mux_dataout = sel_wire[0..0] & data_wire[115..115] # !(sel_wire[0..0]) & data_wire[45..45]; 
	l1_w45_n1_mux_dataout = sel_wire[0..0] & data_wire[255..255] # !(sel_wire[0..0]) & data_wire[185..185]; 
	l1_w46_n0_mux_dataout = sel_wire[0..0] & data_wire[116..116] # !(sel_wire[0..0]) & data_wire[46..46]; 
	l1_w46_n1_mux_dataout = sel_wire[0..0] & data_wire[256..256] # !(sel_wire[0..0]) & data_wire[186..186]; 
	l1_w47_n0_mux_dataout = sel_wire[0..0] & data_wire[117..117] # !(sel_wire[0..0]) & data_wire[47..47]; 
	l1_w47_n1_mux_dataout = sel_wire[0..0] & data_wire[257..257] # !(sel_wire[0..0]) & data_wire[187..187]; 
	l1_w48_n0_mux_dataout = sel_wire[0..0] & data_wire[118..118] # !(sel_wire[0..0]) & data_wire[48..48]; 
	l1_w48_n1_mux_dataout = sel_wire[0..0] & data_wire[258..258] # !(sel_wire[0..0]) & data_wire[188..188]; 
	l1_w49_n0_mux_dataout = sel_wire[0..0] & data_wire[119..119] # !(sel_wire[0..0]) & data_wire[49..49]; 
	l1_w49_n1_mux_dataout = sel_wire[0..0] & data_wire[259..259] # !(sel_wire[0..0]) & data_wire[189..189]; 
	l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[74..74] # !(sel_wire[0..0]) & data_wire[4..4]; 
	l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[214..214] # !(sel_wire[0..0]) & data_wire[144..144]; 
	l1_w50_n0_mux_dataout = sel_wire[0..0] & data_wire[120..120] # !(sel_wire[0..0]) & data_wire[50..50]; 
	l1_w50_n1_mux_dataout = sel_wire[0..0] & data_wire[260..260] # !(sel_wire[0..0]) & data_wire[190..190]; 
	l1_w51_n0_mux_dataout = sel_wire[0..0] & data_wire[121..121] # !(sel_wire[0..0]) & data_wire[51..51]; 
	l1_w51_n1_mux_dataout = sel_wire[0..0] & data_wire[261..261] # !(sel_wire[0..0]) & data_wire[191..191]; 
	l1_w52_n0_mux_dataout = sel_wire[0..0] & data_wire[122..122] # !(sel_wire[0..0]) & data_wire[52..52]; 
	l1_w52_n1_mux_dataout = sel_wire[0..0] & data_wire[262..262] # !(sel_wire[0..0]) & data_wire[192..192]; 
	l1_w53_n0_mux_dataout = sel_wire[0..0] & data_wire[123..123] # !(sel_wire[0..0]) & data_wire[53..53]; 
	l1_w53_n1_mux_dataout = sel_wire[0..0] & data_wire[263..263] # !(sel_wire[0..0]) & data_wire[193..193]; 
	l1_w54_n0_mux_dataout = sel_wire[0..0] & data_wire[124..124] # !(sel_wire[0..0]) & data_wire[54..54]; 
	l1_w54_n1_mux_dataout = sel_wire[0..0] & data_wire[264..264] # !(sel_wire[0..0]) & data_wire[194..194]; 
	l1_w55_n0_mux_dataout = sel_wire[0..0] & data_wire[125..125] # !(sel_wire[0..0]) & data_wire[55..55]; 
	l1_w55_n1_mux_dataout = sel_wire[0..0] & data_wire[265..265] # !(sel_wire[0..0]) & data_wire[195..195]; 
	l1_w56_n0_mux_dataout = sel_wire[0..0] & data_wire[126..126] # !(sel_wire[0..0]) & data_wire[56..56]; 
	l1_w56_n1_mux_dataout = sel_wire[0..0] & data_wire[266..266] # !(sel_wire[0..0]) & data_wire[196..196]; 
	l1_w57_n0_mux_dataout = sel_wire[0..0] & data_wire[127..127] # !(sel_wire[0..0]) & data_wire[57..57]; 
	l1_w57_n1_mux_dataout = sel_wire[0..0] & data_wire[267..267] # !(sel_wire[0..0]) & data_wire[197..197]; 
	l1_w58_n0_mux_dataout = sel_wire[0..0] & data_wire[128..128] # !(sel_wire[0..0]) & data_wire[58..58]; 
	l1_w58_n1_mux_dataout = sel_wire[0..0] & data_wire[268..268] # !(sel_wire[0..0]) & data_wire[198..198]; 
	l1_w59_n0_mux_dataout = sel_wire[0..0] & data_wire[129..129] # !(sel_wire[0..0]) & data_wire[59..59]; 
	l1_w59_n1_mux_dataout = sel_wire[0..0] & data_wire[269..269] # !(sel_wire[0..0]) & data_wire[199..199]; 
	l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[75..75] # !(sel_wire[0..0]) & data_wire[5..5]; 
	l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[215..215] # !(sel_wire[0..0]) & data_wire[145..145]; 
	l1_w60_n0_mux_dataout = sel_wire[0..0] & data_wire[130..130] # !(sel_wire[0..0]) & data_wire[60..60]; 
	l1_w60_n1_mux_dataout = sel_wire[0..0] & data_wire[270..270] # !(sel_wire[0..0]) & data_wire[200..200]; 
	l1_w61_n0_mux_dataout = sel_wire[0..0] & data_wire[131..131] # !(sel_wire[0..0]) & data_wire[61..61]; 
	l1_w61_n1_mux_dataout = sel_wire[0..0] & data_wire[271..271] # !(sel_wire[0..0]) & data_wire[201..201]; 
	l1_w62_n0_mux_dataout = sel_wire[0..0] & data_wire[132..132] # !(sel_wire[0..0]) & data_wire[62..62]; 
	l1_w62_n1_mux_dataout = sel_wire[0..0] & data_wire[272..272] # !(sel_wire[0..0]) & data_wire[202..202]; 
	l1_w63_n0_mux_dataout = sel_wire[0..0] & data_wire[133..133] # !(sel_wire[0..0]) & data_wire[63..63]; 
	l1_w63_n1_mux_dataout = sel_wire[0..0] & data_wire[273..273] # !(sel_wire[0..0]) & data_wire[203..203]; 
	l1_w64_n0_mux_dataout = sel_wire[0..0] & data_wire[134..134] # !(sel_wire[0..0]) & data_wire[64..64]; 
	l1_w64_n1_mux_dataout = sel_wire[0..0] & data_wire[274..274] # !(sel_wire[0..0]) & data_wire[204..204]; 
	l1_w65_n0_mux_dataout = sel_wire[0..0] & data_wire[135..135] # !(sel_wire[0..0]) & data_wire[65..65]; 
	l1_w65_n1_mux_dataout = sel_wire[0..0] & data_wire[275..275] # !(sel_wire[0..0]) & data_wire[205..205]; 
	l1_w66_n0_mux_dataout = sel_wire[0..0] & data_wire[136..136] # !(sel_wire[0..0]) & data_wire[66..66]; 
	l1_w66_n1_mux_dataout = sel_wire[0..0] & data_wire[276..276] # !(sel_wire[0..0]) & data_wire[206..206]; 
	l1_w67_n0_mux_dataout = sel_wire[0..0] & data_wire[137..137] # !(sel_wire[0..0]) & data_wire[67..67]; 
	l1_w67_n1_mux_dataout = sel_wire[0..0] & data_wire[277..277] # !(sel_wire[0..0]) & data_wire[207..207]; 
	l1_w68_n0_mux_dataout = sel_wire[0..0] & data_wire[138..138] # !(sel_wire[0..0]) & data_wire[68..68]; 
	l1_w68_n1_mux_dataout = sel_wire[0..0] & data_wire[278..278] # !(sel_wire[0..0]) & data_wire[208..208]; 
	l1_w69_n0_mux_dataout = sel_wire[0..0] & data_wire[139..139] # !(sel_wire[0..0]) & data_wire[69..69]; 
	l1_w69_n1_mux_dataout = sel_wire[0..0] & data_wire[279..279] # !(sel_wire[0..0]) & data_wire[209..209]; 
	l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[76..76] # !(sel_wire[0..0]) & data_wire[6..6]; 
	l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[216..216] # !(sel_wire[0..0]) & data_wire[146..146]; 
	l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[77..77] # !(sel_wire[0..0]) & data_wire[7..7]; 
	l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[217..217] # !(sel_wire[0..0]) & data_wire[147..147]; 
	l1_w8_n0_mux_dataout = sel_wire[0..0] & data_wire[78..78] # !(sel_wire[0..0]) & data_wire[8..8]; 
	l1_w8_n1_mux_dataout = sel_wire[0..0] & data_wire[218..218] # !(sel_wire[0..0]) & data_wire[148..148]; 
	l1_w9_n0_mux_dataout = sel_wire[0..0] & data_wire[79..79] # !(sel_wire[0..0]) & data_wire[9..9]; 
	l1_w9_n1_mux_dataout = sel_wire[0..0] & data_wire[219..219] # !(sel_wire[0..0]) & data_wire[149..149]; 
	l2_w0_n0_mux_dataout = sel_wire[3..3] & data_wire[281..281] # !(sel_wire[3..3]) & data_wire[280..280]; 
	l2_w10_n0_mux_dataout = sel_wire[3..3] & data_wire[301..301] # !(sel_wire[3..3]) & data_wire[300..300]; 
	l2_w11_n0_mux_dataout = sel_wire[3..3] & data_wire[303..303] # !(sel_wire[3..3]) & data_wire[302..302]; 
	l2_w12_n0_mux_dataout = sel_wire[3..3] & data_wire[305..305] # !(sel_wire[3..3]) & data_wire[304..304]; 
	l2_w13_n0_mux_dataout = sel_wire[3..3] & data_wire[307..307] # !(sel_wire[3..3]) & data_wire[306..306]; 
	l2_w14_n0_mux_dataout = sel_wire[3..3] & data_wire[309..309] # !(sel_wire[3..3]) & data_wire[308..308]; 
	l2_w15_n0_mux_dataout = sel_wire[3..3] & data_wire[311..311] # !(sel_wire[3..3]) & data_wire[310..310]; 
	l2_w16_n0_mux_dataout = sel_wire[3..3] & data_wire[313..313] # !(sel_wire[3..3]) & data_wire[312..312]; 
	l2_w17_n0_mux_dataout = sel_wire[3..3] & data_wire[315..315] # !(sel_wire[3..3]) & data_wire[314..314]; 
	l2_w18_n0_mux_dataout = sel_wire[3..3] & data_wire[317..317] # !(sel_wire[3..3]) & data_wire[316..316]; 
	l2_w19_n0_mux_dataout = sel_wire[3..3] & data_wire[319..319] # !(sel_wire[3..3]) & data_wire[318..318]; 
	l2_w1_n0_mux_dataout = sel_wire[3..3] & data_wire[283..283] # !(sel_wire[3..3]) & data_wire[282..282]; 
	l2_w20_n0_mux_dataout = sel_wire[3..3] & data_wire[321..321] # !(sel_wire[3..3]) & data_wire[320..320]; 
	l2_w21_n0_mux_dataout = sel_wire[3..3] & data_wire[323..323] # !(sel_wire[3..3]) & data_wire[322..322]; 
	l2_w22_n0_mux_dataout = sel_wire[3..3] & data_wire[325..325] # !(sel_wire[3..3]) & data_wire[324..324]; 
	l2_w23_n0_mux_dataout = sel_wire[3..3] & data_wire[327..327] # !(sel_wire[3..3]) & data_wire[326..326]; 
	l2_w24_n0_mux_dataout = sel_wire[3..3] & data_wire[329..329] # !(sel_wire[3..3]) & data_wire[328..328]; 
	l2_w25_n0_mux_dataout = sel_wire[3..3] & data_wire[331..331] # !(sel_wire[3..3]) & data_wire[330..330]; 
	l2_w26_n0_mux_dataout = sel_wire[3..3] & data_wire[333..333] # !(sel_wire[3..3]) & data_wire[332..332]; 
	l2_w27_n0_mux_dataout = sel_wire[3..3] & data_wire[335..335] # !(sel_wire[3..3]) & data_wire[334..334]; 
	l2_w28_n0_mux_dataout = sel_wire[3..3] & data_wire[337..337] # !(sel_wire[3..3]) & data_wire[336..336]; 
	l2_w29_n0_mux_dataout = sel_wire[3..3] & data_wire[339..339] # !(sel_wire[3..3]) & data_wire[338..338]; 
	l2_w2_n0_mux_dataout = sel_wire[3..3] & data_wire[285..285] # !(sel_wire[3..3]) & data_wire[284..284]; 
	l2_w30_n0_mux_dataout = sel_wire[3..3] & data_wire[341..341] # !(sel_wire[3..3]) & data_wire[340..340]; 
	l2_w31_n0_mux_dataout = sel_wire[3..3] & data_wire[343..343] # !(sel_wire[3..3]) & data_wire[342..342]; 
	l2_w32_n0_mux_dataout = sel_wire[3..3] & data_wire[345..345] # !(sel_wire[3..3]) & data_wire[344..344]; 
	l2_w33_n0_mux_dataout = sel_wire[3..3] & data_wire[347..347] # !(sel_wire[3..3]) & data_wire[346..346]; 
	l2_w34_n0_mux_dataout = sel_wire[3..3] & data_wire[349..349] # !(sel_wire[3..3]) & data_wire[348..348]; 
	l2_w35_n0_mux_dataout = sel_wire[3..3] & data_wire[351..351] # !(sel_wire[3..3]) & data_wire[350..350]; 
	l2_w36_n0_mux_dataout = sel_wire[3..3] & data_wire[353..353] # !(sel_wire[3..3]) & data_wire[352..352]; 
	l2_w37_n0_mux_dataout = sel_wire[3..3] & data_wire[355..355] # !(sel_wire[3..3]) & data_wire[354..354]; 
	l2_w38_n0_mux_dataout = sel_wire[3..3] & data_wire[357..357] # !(sel_wire[3..3]) & data_wire[356..356]; 
	l2_w39_n0_mux_dataout = sel_wire[3..3] & data_wire[359..359] # !(sel_wire[3..3]) & data_wire[358..358]; 
	l2_w3_n0_mux_dataout = sel_wire[3..3] & data_wire[287..287] # !(sel_wire[3..3]) & data_wire[286..286]; 
	l2_w40_n0_mux_dataout = sel_wire[3..3] & data_wire[361..361] # !(sel_wire[3..3]) & data_wire[360..360]; 
	l2_w41_n0_mux_dataout = sel_wire[3..3] & data_wire[363..363] # !(sel_wire[3..3]) & data_wire[362..362]; 
	l2_w42_n0_mux_dataout = sel_wire[3..3] & data_wire[365..365] # !(sel_wire[3..3]) & data_wire[364..364]; 
	l2_w43_n0_mux_dataout = sel_wire[3..3] & data_wire[367..367] # !(sel_wire[3..3]) & data_wire[366..366]; 
	l2_w44_n0_mux_dataout = sel_wire[3..3] & data_wire[369..369] # !(sel_wire[3..3]) & data_wire[368..368]; 
	l2_w45_n0_mux_dataout = sel_wire[3..3] & data_wire[371..371] # !(sel_wire[3..3]) & data_wire[370..370]; 
	l2_w46_n0_mux_dataout = sel_wire[3..3] & data_wire[373..373] # !(sel_wire[3..3]) & data_wire[372..372]; 
	l2_w47_n0_mux_dataout = sel_wire[3..3] & data_wire[375..375] # !(sel_wire[3..3]) & data_wire[374..374]; 
	l2_w48_n0_mux_dataout = sel_wire[3..3] & data_wire[377..377] # !(sel_wire[3..3]) & data_wire[376..376]; 
	l2_w49_n0_mux_dataout = sel_wire[3..3] & data_wire[379..379] # !(sel_wire[3..3]) & data_wire[378..378]; 
	l2_w4_n0_mux_dataout = sel_wire[3..3] & data_wire[289..289] # !(sel_wire[3..3]) & data_wire[288..288]; 
	l2_w50_n0_mux_dataout = sel_wire[3..3] & data_wire[381..381] # !(sel_wire[3..3]) & data_wire[380..380]; 
	l2_w51_n0_mux_dataout = sel_wire[3..3] & data_wire[383..383] # !(sel_wire[3..3]) & data_wire[382..382]; 
	l2_w52_n0_mux_dataout = sel_wire[3..3] & data_wire[385..385] # !(sel_wire[3..3]) & data_wire[384..384]; 
	l2_w53_n0_mux_dataout = sel_wire[3..3] & data_wire[387..387] # !(sel_wire[3..3]) & data_wire[386..386]; 
	l2_w54_n0_mux_dataout = sel_wire[3..3] & data_wire[389..389] # !(sel_wire[3..3]) & data_wire[388..388]; 
	l2_w55_n0_mux_dataout = sel_wire[3..3] & data_wire[391..391] # !(sel_wire[3..3]) & data_wire[390..390]; 
	l2_w56_n0_mux_dataout = sel_wire[3..3] & data_wire[393..393] # !(sel_wire[3..3]) & data_wire[392..392]; 
	l2_w57_n0_mux_dataout = sel_wire[3..3] & data_wire[395..395] # !(sel_wire[3..3]) & data_wire[394..394]; 
	l2_w58_n0_mux_dataout = sel_wire[3..3] & data_wire[397..397] # !(sel_wire[3..3]) & data_wire[396..396]; 
	l2_w59_n0_mux_dataout = sel_wire[3..3] & data_wire[399..399] # !(sel_wire[3..3]) & data_wire[398..398]; 
	l2_w5_n0_mux_dataout = sel_wire[3..3] & data_wire[291..291] # !(sel_wire[3..3]) & data_wire[290..290]; 
	l2_w60_n0_mux_dataout = sel_wire[3..3] & data_wire[401..401] # !(sel_wire[3..3]) & data_wire[400..400]; 
	l2_w61_n0_mux_dataout = sel_wire[3..3] & data_wire[403..403] # !(sel_wire[3..3]) & data_wire[402..402]; 
	l2_w62_n0_mux_dataout = sel_wire[3..3] & data_wire[405..405] # !(sel_wire[3..3]) & data_wire[404..404]; 
	l2_w63_n0_mux_dataout = sel_wire[3..3] & data_wire[407..407] # !(sel_wire[3..3]) & data_wire[406..406]; 
	l2_w64_n0_mux_dataout = sel_wire[3..3] & data_wire[409..409] # !(sel_wire[3..3]) & data_wire[408..408]; 
	l2_w65_n0_mux_dataout = sel_wire[3..3] & data_wire[411..411] # !(sel_wire[3..3]) & data_wire[410..410]; 
	l2_w66_n0_mux_dataout = sel_wire[3..3] & data_wire[413..413] # !(sel_wire[3..3]) & data_wire[412..412]; 
	l2_w67_n0_mux_dataout = sel_wire[3..3] & data_wire[415..415] # !(sel_wire[3..3]) & data_wire[414..414]; 
	l2_w68_n0_mux_dataout = sel_wire[3..3] & data_wire[417..417] # !(sel_wire[3..3]) & data_wire[416..416]; 
	l2_w69_n0_mux_dataout = sel_wire[3..3] & data_wire[419..419] # !(sel_wire[3..3]) & data_wire[418..418]; 
	l2_w6_n0_mux_dataout = sel_wire[3..3] & data_wire[293..293] # !(sel_wire[3..3]) & data_wire[292..292]; 
	l2_w7_n0_mux_dataout = sel_wire[3..3] & data_wire[295..295] # !(sel_wire[3..3]) & data_wire[294..294]; 
	l2_w8_n0_mux_dataout = sel_wire[3..3] & data_wire[297..297] # !(sel_wire[3..3]) & data_wire[296..296]; 
	l2_w9_n0_mux_dataout = sel_wire[3..3] & data_wire[299..299] # !(sel_wire[3..3]) & data_wire[298..298]; 
	data_wire[] = ( l1_w69_n1_mux_dataout, l1_w69_n0_mux_dataout, l1_w68_n1_mux_dataout, l1_w68_n0_mux_dataout, l1_w67_n1_mux_dataout, l1_w67_n0_mux_dataout, l1_w66_n1_mux_dataout, l1_w66_n0_mux_dataout, l1_w65_n1_mux_dataout, l1_w65_n0_mux_dataout, l1_w64_n1_mux_dataout, l1_w64_n0_mux_dataout, l1_w63_n1_mux_dataout, l1_w63_n0_mux_dataout, l1_w62_n1_mux_dataout, l1_w62_n0_mux_dataout, l1_w61_n1_mux_dataout, l1_w61_n0_mux_dataout, l1_w60_n1_mux_dataout, l1_w60_n0_mux_dataout, l1_w59_n1_mux_dataout, l1_w59_n0_mux_dataout, l1_w58_n1_mux_dataout, l1_w58_n0_mux_dataout, l1_w57_n1_mux_dataout, l1_w57_n0_mux_dataout, l1_w56_n1_mux_dataout, l1_w56_n0_mux_dataout, l1_w55_n1_mux_dataout, l1_w55_n0_mux_dataout, l1_w54_n1_mux_dataout, l1_w54_n0_mux_dataout, l1_w53_n1_mux_dataout, l1_w53_n0_mux_dataout, l1_w52_n1_mux_dataout, l1_w52_n0_mux_dataout, l1_w51_n1_mux_dataout, l1_w51_n0_mux_dataout, l1_w50_n1_mux_dataout, l1_w50_n0_mux_dataout, l1_w49_n1_mux_dataout, l1_w49_n0_mux_dataout, l1_w48_n1_mux_dataout, l1_w48_n0_mux_dataout, l1_w47_n1_mux_dataout, l1_w47_n0_mux_dataout, l1_w46_n1_mux_dataout, l1_w46_n0_mux_dataout, l1_w45_n1_mux_dataout, l1_w45_n0_mux_dataout, l1_w44_n1_mux_dataout, l1_w44_n0_mux_dataout, l1_w43_n1_mux_dataout, l1_w43_n0_mux_dataout, l1_w42_n1_mux_dataout, l1_w42_n0_mux_dataout, l1_w41_n1_mux_dataout, l1_w41_n0_mux_dataout, l1_w40_n1_mux_dataout, l1_w40_n0_mux_dataout, l1_w39_n1_mux_dataout, l1_w39_n0_mux_dataout, l1_w38_n1_mux_dataout, l1_w38_n0_mux_dataout, l1_w37_n1_mux_dataout, l1_w37_n0_mux_dataout, l1_w36_n1_mux_dataout, l1_w36_n0_mux_dataout, l1_w35_n1_mux_dataout, l1_w35_n0_mux_dataout, l1_w34_n1_mux_dataout, l1_w34_n0_mux_dataout, l1_w33_n1_mux_dataout, l1_w33_n0_mux_dataout, l1_w32_n1_mux_dataout, l1_w32_n0_mux_dataout, l1_w31_n1_mux_dataout, l1_w31_n0_mux_dataout, l1_w30_n1_mux_dataout, l1_w30_n0_mux_dataout, l1_w29_n1_mux_dataout, l1_w29_n0_mux_dataout, l1_w28_n1_mux_dataout, l1_w28_n0_mux_dataout, l1_w27_n1_mux_dataout, l1_w27_n0_mux_dataout, l1_w26_n1_mux_dataout, l1_w26_n0_mux_dataout, l1_w25_n1_mux_dataout, l1_w25_n0_mux_dataout, l1_w24_n1_mux_dataout, l1_w24_n0_mux_dataout, l1_w23_n1_mux_dataout, l1_w23_n0_mux_dataout, l1_w22_n1_mux_dataout, l1_w22_n0_mux_dataout, l1_w21_n1_mux_dataout, l1_w21_n0_mux_dataout, l1_w20_n1_mux_dataout, l1_w20_n0_mux_dataout, l1_w19_n1_mux_dataout, l1_w19_n0_mux_dataout, l1_w18_n1_mux_dataout, l1_w18_n0_mux_dataout, l1_w17_n1_mux_dataout, l1_w17_n0_mux_dataout, l1_w16_n1_mux_dataout, l1_w16_n0_mux_dataout, l1_w15_n1_mux_dataout, l1_w15_n0_mux_dataout, l1_w14_n1_mux_dataout, l1_w14_n0_mux_dataout, l1_w13_n1_mux_dataout, l1_w13_n0_mux_dataout, l1_w12_n1_mux_dataout, l1_w12_n0_mux_dataout, l1_w11_n1_mux_dataout, l1_w11_n0_mux_dataout, l1_w10_n1_mux_dataout, l1_w10_n0_mux_dataout, l1_w9_n1_mux_dataout, l1_w9_n0_mux_dataout, l1_w8_n1_mux_dataout, l1_w8_n0_mux_dataout, l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]); 
	result[] = result_wire_ext[]; 
	result_wire_ext[] = ( l2_w69_n0_mux_dataout, l2_w68_n0_mux_dataout, l2_w67_n0_mux_dataout, l2_w66_n0_mux_dataout, l2_w65_n0_mux_dataout, l2_w64_n0_mux_dataout, l2_w63_n0_mux_dataout, l2_w62_n0_mux_dataout, l2_w61_n0_mux_dataout, l2_w60_n0_mux_dataout, l2_w59_n0_mux_dataout, l2_w58_n0_mux_dataout, l2_w57_n0_mux_dataout, l2_w56_n0_mux_dataout, l2_w55_n0_mux_dataout, l2_w54_n0_mux_dataout, l2_w53_n0_mux_dataout, l2_w52_n0_mux_dataout, l2_w51_n0_mux_dataout, l2_w50_n0_mux_dataout, l2_w49_n0_mux_dataout, l2_w48_n0_mux_dataout, l2_w47_n0_mux_dataout, l2_w46_n0_mux_dataout, l2_w45_n0_mux_dataout, l2_w44_n0_mux_dataout, l2_w43_n0_mux_dataout, l2_w42_n0_mux_dataout, l2_w41_n0_mux_dataout, l2_w40_n0_mux_dataout, l2_w39_n0_mux_dataout, l2_w38_n0_mux_dataout, l2_w37_n0_mux_dataout, l2_w36_n0_mux_dataout, l2_w35_n0_mux_dataout, l2_w34_n0_mux_dataout, l2_w33_n0_mux_dataout, l2_w32_n0_mux_dataout, l2_w31_n0_mux_dataout, l2_w30_n0_mux_dataout, l2_w29_n0_mux_dataout, l2_w28_n0_mux_dataout, l2_w27_n0_mux_dataout, l2_w26_n0_mux_dataout, l2_w25_n0_mux_dataout, l2_w24_n0_mux_dataout, l2_w23_n0_mux_dataout, l2_w22_n0_mux_dataout, l2_w21_n0_mux_dataout, l2_w20_n0_mux_dataout, l2_w19_n0_mux_dataout, l2_w18_n0_mux_dataout, l2_w17_n0_mux_dataout, l2_w16_n0_mux_dataout, l2_w15_n0_mux_dataout, l2_w14_n0_mux_dataout, l2_w13_n0_mux_dataout, l2_w12_n0_mux_dataout, l2_w11_n0_mux_dataout, l2_w10_n0_mux_dataout, l2_w9_n0_mux_dataout, l2_w8_n0_mux_dataout, l2_w7_n0_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n0_mux_dataout); 
	sel_wire[] = ( sel[1..1], B"00", sel[0..0]); 
END; 
--VALID FILE