www.pudn.com > DS28E01_final.zip > decode_6pa.tdf, change:2014-07-31,size:2268b


--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II" LPM_DECODES=4 LPM_WIDTH=2 data enable eq 
--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_compare 2009:10:21:21:22:16:SJ cbx_lpm_decode 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2009 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
 
--synthesis_resources = lut 4  
SUBDESIGN decode_6pa 
(  
	data[1..0]	:	input; 
	enable	:	input; 
	eq[3..0]	:	output; 
)  
VARIABLE  
	data_wire[1..0]	: WIRE; 
	enable_wire	: WIRE; 
	eq_node[3..0]	: WIRE; 
	eq_wire[3..0]	: WIRE; 
	w_anode324w[2..0]	: WIRE; 
	w_anode337w[2..0]	: WIRE; 
	w_anode345w[2..0]	: WIRE; 
	w_anode353w[2..0]	: WIRE; 
 
BEGIN  
	data_wire[] = data[]; 
	enable_wire = enable; 
	eq[] = eq_node[]; 
	eq_node[3..0] = eq_wire[3..0]; 
	eq_wire[] = ( w_anode353w[2..2], w_anode345w[2..2], w_anode337w[2..2], w_anode324w[2..2]); 
	w_anode324w[] = ( (w_anode324w[1..1] & (! data_wire[1..1])), (w_anode324w[0..0] & (! data_wire[0..0])), enable_wire); 
	w_anode337w[] = ( (w_anode337w[1..1] & (! data_wire[1..1])), (w_anode337w[0..0] & data_wire[0..0]), enable_wire); 
	w_anode345w[] = ( (w_anode345w[1..1] & data_wire[1..1]), (w_anode345w[0..0] & (! data_wire[0..0])), enable_wire); 
	w_anode353w[] = ( (w_anode353w[1..1] & data_wire[1..1]), (w_anode353w[0..0] & data_wire[0..0]), enable_wire); 
END; 
--VALID FILE