www.pudn.com > DS28E01_final.zip > cntr_3di.tdf, change:2014-07-31,size:4753b


--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II" lpm_modulus=70 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=7 clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 
--VERSION_BEGIN 9.1 cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_compare 2009:10:21:21:22:16:SJ cbx_lpm_counter 2009:10:21:21:22:16:SJ cbx_lpm_decode 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2009 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION cmpr_ddc (dataa[6..0], datab[6..0]) 
RETURNS ( aeb); 
FUNCTION stratixii_lcell_comb (cin, dataa, datab, datac, datad, datae, dataf, datag, sharein) 
WITH ( EXTENDED_LUT, LUT_MASK, SHARED_ARITH) 
RETURNS ( combout, cout, shareout, sumout); 
FUNCTION stratixii_lcell_ff (aclr, adatasdata, aload, clk, datain, ena, sclr, sload) 
WITH ( x_on_violation) 
RETURNS ( regout); 
 
--synthesis_resources = lut 7 reg 7  
SUBDESIGN cntr_3di 
(  
	clock	:	input; 
	q[6..0]	:	output; 
	sclr	:	input; 
)  
VARIABLE  
	cmpr2 : cmpr_ddc; 
	counter_comb_bita0 : stratixii_lcell_comb 
		WITH ( 
			EXTENDED_LUT = "off", 
			LUT_MASK = "000000000000FF00", 
			SHARED_ARITH = "off" 
		); 
	counter_comb_bita1 : stratixii_lcell_comb 
		WITH ( 
			EXTENDED_LUT = "off", 
			LUT_MASK = "0000FF000000FF00", 
			SHARED_ARITH = "off" 
		); 
	counter_comb_bita2 : stratixii_lcell_comb 
		WITH ( 
			EXTENDED_LUT = "off", 
			LUT_MASK = "0000FF000000FF00", 
			SHARED_ARITH = "off" 
		); 
	counter_comb_bita3 : stratixii_lcell_comb 
		WITH ( 
			EXTENDED_LUT = "off", 
			LUT_MASK = "0000FF000000FF00", 
			SHARED_ARITH = "off" 
		); 
	counter_comb_bita4 : stratixii_lcell_comb 
		WITH ( 
			EXTENDED_LUT = "off", 
			LUT_MASK = "0000FF000000FF00", 
			SHARED_ARITH = "off" 
		); 
	counter_comb_bita5 : stratixii_lcell_comb 
		WITH ( 
			EXTENDED_LUT = "off", 
			LUT_MASK = "0000FF000000FF00", 
			SHARED_ARITH = "off" 
		); 
	counter_comb_bita6 : stratixii_lcell_comb 
		WITH ( 
			EXTENDED_LUT = "off", 
			LUT_MASK = "0000FF000000FF00", 
			SHARED_ARITH = "off" 
		); 
	counter_reg_bit1a[6..0] : stratixii_lcell_ff; 
	aclr_actual	: WIRE; 
	clk_en	: NODE; 
	cnt_en	: NODE; 
	compare_result	: WIRE; 
	cout_actual	: WIRE; 
	data[6..0]	: NODE; 
	external_cin	: WIRE; 
	lsb_cin	: WIRE; 
	modulus_bus[6..0]	: WIRE; 
	modulus_trigger	: WIRE; 
	s_val[6..0]	: WIRE; 
	safe_q[6..0]	: WIRE; 
	sload	: NODE; 
	sset	: NODE; 
	time_to_clear	: WIRE; 
	updown_dir	: WIRE; 
	updown_lsb	: WIRE; 
	updown_other_bits	: WIRE; 
 
BEGIN  
	cmpr2.dataa[] = safe_q[]; 
	cmpr2.datab[] = modulus_bus[]; 
	counter_comb_bita[6..0].cin = ( counter_comb_bita[5..0].cout, lsb_cin); 
	counter_comb_bita[6..0].datad = ( counter_reg_bit1a[6..0].regout); 
	counter_comb_bita[6..0].dataf = ( updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_lsb); 
	counter_reg_bit1a[].aclr = aclr_actual; 
	counter_reg_bit1a[].adatasdata = ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))); 
	counter_reg_bit1a[].clk = clock; 
	counter_reg_bit1a[].datain = ( counter_comb_bita[6..0].sumout); 
	counter_reg_bit1a[].ena = (clk_en & (((cnt_en # sclr) # sset) # sload)); 
	counter_reg_bit1a[].sclr = sclr; 
	counter_reg_bit1a[].sload = ((sset # sload) # modulus_trigger); 
	aclr_actual = B"0"; 
	clk_en = VCC; 
	cnt_en = VCC; 
	compare_result = cmpr2.aeb; 
	cout_actual = (((! counter_comb_bita[6].cout) $ updown_other_bits) # (time_to_clear & updown_dir)); 
	data[] = GND; 
	external_cin = B"1"; 
	lsb_cin = B"0"; 
	modulus_bus[] = B"1000101"; 
	modulus_trigger = cout_actual; 
	q[] = safe_q[]; 
	s_val[] = B"1111111"; 
	safe_q[] = counter_reg_bit1a[].regout; 
	sload = GND; 
	sset = GND; 
	time_to_clear = compare_result; 
	updown_dir = B"1"; 
	updown_lsb = updown_dir; 
	updown_other_bits = ((! external_cin) # updown_dir); 
END; 
--VALID FILE