www.pudn.com > DS28E01_final.zip > altsyncram_t4b2.tdf, change:2007-09-13,size:48516b


--altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" ENABLE_RUNTIME_MOD="NO" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE="Enabler_DS28E01.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK1" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 WIDTHAD_B=8 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 
--VERSION_BEGIN 7.2 cbx_altsyncram 2007:06:28:16:56:28:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:07:06:02:56:06:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:06:25:16:16:52:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2007 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) 
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) 
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); 
 
--synthesis_resources = M9K 2  
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; 
 
SUBDESIGN altsyncram_t4b2 
(  
	address_a[7..0]	:	input; 
	address_b[7..0]	:	input; 
	clock0	:	input; 
	clock1	:	input; 
	data_a[31..0]	:	input; 
	data_b[31..0]	:	input; 
	q_a[31..0]	:	output; 
	q_b[31..0]	:	output; 
	wren_a	:	input; 
	wren_b	:	input; 
)  
VARIABLE  
	ram_block3a0 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 0, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 0, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a1 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 1, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 1, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a2 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 2, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 2, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a3 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 3, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 3, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a4 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 4, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 4, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a5 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 5, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 5, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a6 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 6, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 6, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a7 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 7, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 7, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a8 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 8, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 8, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a9 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 9, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 9, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a10 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 10, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 10, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a11 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 11, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 11, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a12 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 12, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 12, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a13 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 13, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 13, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a14 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 14, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 14, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a15 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 15, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 15, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a16 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 16, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 16, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a17 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 17, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 17, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a18 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 18, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 18, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a19 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 19, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 19, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a20 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 20, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 20, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a21 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 21, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 21, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a22 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 22, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 22, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a23 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 23, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 23, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a24 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 24, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 24, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a25 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 25, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 25, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a26 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 26, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 26, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a27 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 27, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 27, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a28 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 28, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 28, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a29 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 29, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 29, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a30 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 30, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 30, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block3a31 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "none", 
			CLK0_INPUT_CLOCK_ENABLE = "none", 
			CLK1_CORE_CLOCK_ENABLE = "none", 
			CLK1_INPUT_CLOCK_ENABLE = "none", 
			CONNECTIVITY_CHECKING = "OFF", 
			INIT_FILE = "Enabler_DS28E01.mif", 
			INIT_FILE_LAYOUT = "port_a", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "bidir_dual_port", 
			PORT_A_ADDRESS_WIDTH = 8, 
			PORT_A_DATA_OUT_CLEAR = "none", 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 31, 
			PORT_A_LAST_ADDRESS = 255, 
			PORT_A_LOGICAL_RAM_DEPTH = 256, 
			PORT_A_LOGICAL_RAM_WIDTH = 32, 
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 8, 
			PORT_B_DATA_IN_CLOCK = "clock1", 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 31, 
			PORT_B_LAST_ADDRESS = 255, 
			PORT_B_LOGICAL_RAM_DEPTH = 256, 
			PORT_B_LOGICAL_RAM_WIDTH = 32, 
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", 
			PORT_B_READ_ENABLE_CLOCK = "clock1", 
			PORT_B_WRITE_ENABLE_CLOCK = "clock1", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	address_a_wire[7..0]	: WIRE; 
	address_b_wire[7..0]	: WIRE; 
 
BEGIN  
	ram_block3a[31..0].clk0 = clock0; 
	ram_block3a[31..0].clk1 = clock1; 
	ram_block3a[31..0].portaaddr[] = ( address_a_wire[7..0]); 
	ram_block3a[0].portadatain[] = ( data_a[0..0]); 
	ram_block3a[1].portadatain[] = ( data_a[1..1]); 
	ram_block3a[2].portadatain[] = ( data_a[2..2]); 
	ram_block3a[3].portadatain[] = ( data_a[3..3]); 
	ram_block3a[4].portadatain[] = ( data_a[4..4]); 
	ram_block3a[5].portadatain[] = ( data_a[5..5]); 
	ram_block3a[6].portadatain[] = ( data_a[6..6]); 
	ram_block3a[7].portadatain[] = ( data_a[7..7]); 
	ram_block3a[8].portadatain[] = ( data_a[8..8]); 
	ram_block3a[9].portadatain[] = ( data_a[9..9]); 
	ram_block3a[10].portadatain[] = ( data_a[10..10]); 
	ram_block3a[11].portadatain[] = ( data_a[11..11]); 
	ram_block3a[12].portadatain[] = ( data_a[12..12]); 
	ram_block3a[13].portadatain[] = ( data_a[13..13]); 
	ram_block3a[14].portadatain[] = ( data_a[14..14]); 
	ram_block3a[15].portadatain[] = ( data_a[15..15]); 
	ram_block3a[16].portadatain[] = ( data_a[16..16]); 
	ram_block3a[17].portadatain[] = ( data_a[17..17]); 
	ram_block3a[18].portadatain[] = ( data_a[18..18]); 
	ram_block3a[19].portadatain[] = ( data_a[19..19]); 
	ram_block3a[20].portadatain[] = ( data_a[20..20]); 
	ram_block3a[21].portadatain[] = ( data_a[21..21]); 
	ram_block3a[22].portadatain[] = ( data_a[22..22]); 
	ram_block3a[23].portadatain[] = ( data_a[23..23]); 
	ram_block3a[24].portadatain[] = ( data_a[24..24]); 
	ram_block3a[25].portadatain[] = ( data_a[25..25]); 
	ram_block3a[26].portadatain[] = ( data_a[26..26]); 
	ram_block3a[27].portadatain[] = ( data_a[27..27]); 
	ram_block3a[28].portadatain[] = ( data_a[28..28]); 
	ram_block3a[29].portadatain[] = ( data_a[29..29]); 
	ram_block3a[30].portadatain[] = ( data_a[30..30]); 
	ram_block3a[31].portadatain[] = ( data_a[31..31]); 
	ram_block3a[31..0].portare = B"11111111111111111111111111111111"; 
	ram_block3a[31..0].portawe = wren_a; 
	ram_block3a[31..0].portbaddr[] = ( address_b_wire[7..0]); 
	ram_block3a[0].portbdatain[] = ( data_b[0..0]); 
	ram_block3a[1].portbdatain[] = ( data_b[1..1]); 
	ram_block3a[2].portbdatain[] = ( data_b[2..2]); 
	ram_block3a[3].portbdatain[] = ( data_b[3..3]); 
	ram_block3a[4].portbdatain[] = ( data_b[4..4]); 
	ram_block3a[5].portbdatain[] = ( data_b[5..5]); 
	ram_block3a[6].portbdatain[] = ( data_b[6..6]); 
	ram_block3a[7].portbdatain[] = ( data_b[7..7]); 
	ram_block3a[8].portbdatain[] = ( data_b[8..8]); 
	ram_block3a[9].portbdatain[] = ( data_b[9..9]); 
	ram_block3a[10].portbdatain[] = ( data_b[10..10]); 
	ram_block3a[11].portbdatain[] = ( data_b[11..11]); 
	ram_block3a[12].portbdatain[] = ( data_b[12..12]); 
	ram_block3a[13].portbdatain[] = ( data_b[13..13]); 
	ram_block3a[14].portbdatain[] = ( data_b[14..14]); 
	ram_block3a[15].portbdatain[] = ( data_b[15..15]); 
	ram_block3a[16].portbdatain[] = ( data_b[16..16]); 
	ram_block3a[17].portbdatain[] = ( data_b[17..17]); 
	ram_block3a[18].portbdatain[] = ( data_b[18..18]); 
	ram_block3a[19].portbdatain[] = ( data_b[19..19]); 
	ram_block3a[20].portbdatain[] = ( data_b[20..20]); 
	ram_block3a[21].portbdatain[] = ( data_b[21..21]); 
	ram_block3a[22].portbdatain[] = ( data_b[22..22]); 
	ram_block3a[23].portbdatain[] = ( data_b[23..23]); 
	ram_block3a[24].portbdatain[] = ( data_b[24..24]); 
	ram_block3a[25].portbdatain[] = ( data_b[25..25]); 
	ram_block3a[26].portbdatain[] = ( data_b[26..26]); 
	ram_block3a[27].portbdatain[] = ( data_b[27..27]); 
	ram_block3a[28].portbdatain[] = ( data_b[28..28]); 
	ram_block3a[29].portbdatain[] = ( data_b[29..29]); 
	ram_block3a[30].portbdatain[] = ( data_b[30..30]); 
	ram_block3a[31].portbdatain[] = ( data_b[31..31]); 
	ram_block3a[31..0].portbre = B"11111111111111111111111111111111"; 
	ram_block3a[31..0].portbwe = wren_b; 
	address_a_wire[] = address_a[]; 
	address_b_wire[] = address_b[]; 
	q_a[] = ( ram_block3a[31..0].portadataout[0..0]); 
	q_b[] = ( ram_block3a[31..0].portbdataout[0..0]); 
END; 
--VALID FILE