www.pudn.com > DS28E01_final.zip > altsyncram_qns3.tdf, change:2014-07-31,size:51646b


--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_A="NONE" BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" ENABLE_ECC="FALSE" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=0 NUMWORDS_B=0 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M4K" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=10 WIDTH_B=10 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 
--VERSION_BEGIN 9.1 cbx_altsyncram 2009:10:21:21:22:16:SJ cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_compare 2009:10:21:21:22:16:SJ cbx_lpm_decode 2009:10:21:21:22:16:SJ cbx_lpm_mux 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_stratixiii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2009 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION decode_6pa (data[1..0], enable) 
RETURNS ( eq[3..0]); 
FUNCTION mux_vkb (data[39..0], sel[1..0]) 
RETURNS ( result[9..0]); 
FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe) 
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE) 
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); 
 
--synthesis_resources = lut 10 M4K 40 reg 2  
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; 
 
SUBDESIGN altsyncram_qns3 
(  
	address_a[13..0]	:	input; 
	address_b[13..0]	:	input; 
	clock0	:	input; 
	clock1	:	input; 
	clocken1	:	input; 
	data_a[9..0]	:	input; 
	q_b[9..0]	:	output; 
	wren_a	:	input; 
)  
VARIABLE  
	address_reg_b[1..0] : dffe; 
	decode2 : decode_6pa; 
	rden_decode : decode_6pa; 
	mux3 : mux_vkb; 
	ram_block1a0 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 0, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 0, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a1 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 1, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 1, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a2 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 2, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 2, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a3 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 3, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 3, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a4 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 4, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 4, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a5 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 5, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 5, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a6 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 6, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 6, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a7 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 7, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 7, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a8 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 8, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 8, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a9 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 9, 
			PORT_A_LAST_ADDRESS = 4095, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 9, 
			PORT_B_LAST_ADDRESS = 4095, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a10 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 0, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 0, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a11 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 1, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 1, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a12 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 2, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 2, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a13 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 3, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 3, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a14 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 4, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 4, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a15 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 5, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 5, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a16 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 6, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 6, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a17 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 7, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 7, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a18 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 8, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 8, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a19 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 4096, 
			PORT_A_FIRST_BIT_NUMBER = 9, 
			PORT_A_LAST_ADDRESS = 8191, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 4096, 
			PORT_B_FIRST_BIT_NUMBER = 9, 
			PORT_B_LAST_ADDRESS = 8191, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a20 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 0, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 0, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a21 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 1, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 1, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a22 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 2, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 2, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a23 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 3, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 3, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a24 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 4, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 4, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a25 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 5, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 5, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a26 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 6, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 6, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a27 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 7, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 7, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a28 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 8, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 8, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a29 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 8192, 
			PORT_A_FIRST_BIT_NUMBER = 9, 
			PORT_A_LAST_ADDRESS = 12287, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 8192, 
			PORT_B_FIRST_BIT_NUMBER = 9, 
			PORT_B_LAST_ADDRESS = 12287, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a30 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 0, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 0, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a31 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 1, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 1, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a32 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 2, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 2, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a33 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 3, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 3, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a34 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 4, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 4, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a35 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 5, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 5, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a36 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 6, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 6, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a37 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 7, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 7, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a38 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 8, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 8, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	ram_block1a39 : stratixii_ram_block 
		WITH ( 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 12, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_A_FIRST_ADDRESS = 12288, 
			PORT_A_FIRST_BIT_NUMBER = 9, 
			PORT_A_LAST_ADDRESS = 16383, 
			PORT_A_LOGICAL_RAM_DEPTH = 16384, 
			PORT_A_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_ADDRESS_CLOCK = "clock1", 
			PORT_B_ADDRESS_WIDTH = 12, 
			PORT_B_DATA_OUT_CLEAR = "none", 
			PORT_B_DATA_OUT_CLOCK = "none", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", 
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", 
			PORT_B_FIRST_ADDRESS = 12288, 
			PORT_B_FIRST_BIT_NUMBER = 9, 
			PORT_B_LAST_ADDRESS = 16383, 
			PORT_B_LOGICAL_RAM_DEPTH = 16384, 
			PORT_B_LOGICAL_RAM_WIDTH = 10, 
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", 
			POWER_UP_UNINITIALIZED = "false", 
			RAM_BLOCK_TYPE = "M4K" 
		); 
	address_a_wire[13..0]	: WIRE; 
	address_b_sel[1..0]	: WIRE; 
	address_b_wire[13..0]	: WIRE; 
 
BEGIN  
	address_reg_b[].clk = clock1; 
	address_reg_b[].d = address_b_sel[]; 
	address_reg_b[].ena = clocken1; 
	decode2.data[1..0] = address_a_wire[13..12]; 
	decode2.enable = wren_a; 
	rden_decode.data[1..0] = address_b_wire[13..12]; 
	rden_decode.enable = clocken1; 
	mux3.data[] = ( ram_block1a[39..0].portbdataout[0..0]); 
	mux3.sel[] = address_reg_b[].q; 
	ram_block1a[39..0].clk0 = clock0; 
	ram_block1a[39..0].clk1 = clock1; 
	ram_block1a[39..0].ena0 = ( decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); 
	ram_block1a[39..0].ena1 = ( rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..3], rden_decode.eq[3..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..2], rden_decode.eq[2..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]); 
	ram_block1a[39..0].portaaddr[] = ( address_a_wire[11..0]); 
	ram_block1a[0].portadatain[] = ( data_a[0..0]); 
	ram_block1a[1].portadatain[] = ( data_a[1..1]); 
	ram_block1a[2].portadatain[] = ( data_a[2..2]); 
	ram_block1a[3].portadatain[] = ( data_a[3..3]); 
	ram_block1a[4].portadatain[] = ( data_a[4..4]); 
	ram_block1a[5].portadatain[] = ( data_a[5..5]); 
	ram_block1a[6].portadatain[] = ( data_a[6..6]); 
	ram_block1a[7].portadatain[] = ( data_a[7..7]); 
	ram_block1a[8].portadatain[] = ( data_a[8..8]); 
	ram_block1a[9].portadatain[] = ( data_a[9..9]); 
	ram_block1a[10].portadatain[] = ( data_a[0..0]); 
	ram_block1a[11].portadatain[] = ( data_a[1..1]); 
	ram_block1a[12].portadatain[] = ( data_a[2..2]); 
	ram_block1a[13].portadatain[] = ( data_a[3..3]); 
	ram_block1a[14].portadatain[] = ( data_a[4..4]); 
	ram_block1a[15].portadatain[] = ( data_a[5..5]); 
	ram_block1a[16].portadatain[] = ( data_a[6..6]); 
	ram_block1a[17].portadatain[] = ( data_a[7..7]); 
	ram_block1a[18].portadatain[] = ( data_a[8..8]); 
	ram_block1a[19].portadatain[] = ( data_a[9..9]); 
	ram_block1a[20].portadatain[] = ( data_a[0..0]); 
	ram_block1a[21].portadatain[] = ( data_a[1..1]); 
	ram_block1a[22].portadatain[] = ( data_a[2..2]); 
	ram_block1a[23].portadatain[] = ( data_a[3..3]); 
	ram_block1a[24].portadatain[] = ( data_a[4..4]); 
	ram_block1a[25].portadatain[] = ( data_a[5..5]); 
	ram_block1a[26].portadatain[] = ( data_a[6..6]); 
	ram_block1a[27].portadatain[] = ( data_a[7..7]); 
	ram_block1a[28].portadatain[] = ( data_a[8..8]); 
	ram_block1a[29].portadatain[] = ( data_a[9..9]); 
	ram_block1a[30].portadatain[] = ( data_a[0..0]); 
	ram_block1a[31].portadatain[] = ( data_a[1..1]); 
	ram_block1a[32].portadatain[] = ( data_a[2..2]); 
	ram_block1a[33].portadatain[] = ( data_a[3..3]); 
	ram_block1a[34].portadatain[] = ( data_a[4..4]); 
	ram_block1a[35].portadatain[] = ( data_a[5..5]); 
	ram_block1a[36].portadatain[] = ( data_a[6..6]); 
	ram_block1a[37].portadatain[] = ( data_a[7..7]); 
	ram_block1a[38].portadatain[] = ( data_a[8..8]); 
	ram_block1a[39].portadatain[] = ( data_a[9..9]); 
	ram_block1a[39..0].portawe = ( decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); 
	ram_block1a[39..0].portbaddr[] = ( address_b_wire[11..0]); 
	ram_block1a[39..0].portbrewe = B"1111111111111111111111111111111111111111"; 
	address_a_wire[] = address_a[]; 
	address_b_sel[1..0] = address_b[13..12]; 
	address_b_wire[] = address_b[]; 
	q_b[] = mux3.result[]; 
END; 
--VALID FILE