www.pudn.com > ARM(Verilog-a-VHDL).zip > test_wd_reg.out, change:2000-07-08,size:828b


wd_reg Test Log
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WD_Bus_Write=00000000 WD_DBE=1 WD_Load=1 WD_DOUT=xxxxxxxx
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WD_Bus_Write=55555555 WD_DBE=0 WD_Load=0 WD_DOUT=zzzzzzzz
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WD_Bus_Write=aaaaaaaa WD_DBE=0 WD_Load=0 WD_DOUT=zzzzzzzz
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WD_Bus_Write=aaaaaaaa WD_DBE=1 WD_Load=0 WD_DOUT=00000000
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WD_Bus_Write=12121212 WD_DBE=1 WD_Load=1 WD_DOUT=00000000
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WD_Bus_Write=12121212 WD_DBE=1 WD_Load=1 WD_DOUT=00000000
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WD_Bus_Write=55555555 WD_DBE=0 WD_Load=1 WD_DOUT=zzzzzzzz
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WD_Bus_Write=00000000 WD_DBE=0 WD_Load=1 WD_DOUT=zzzzzzzz
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WD_Bus_Write=00000000 WD_DBE=1 WD_Load=1 WD_DOUT=00000000
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WD_Bus_Write=00000000 WD_DBE=1 WD_Load=1 WD_DOUT=00000000
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         10 tests run
--Tests Completed--