www.pudn.com > ARM(Verilog-a-VHDL).zip > test_addr_reg.out, change:2000-07-08,size:650b


addr_reg Test Log
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AR_Bus_Alu=00000000 AR_Bus_PC=55555555 AR_Bus_PC_4=aaaaaaaa AR_Bus_Sel=00 AR_Output_Bus=xxxxxxxx
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AR_Bus_Alu=ffffffff AR_Bus_PC=55555555 AR_Bus_PC_4=aaaaaaaa AR_Bus_Sel=01 AR_Output_Bus=00000000
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AR_Bus_Alu=ffffffff AR_Bus_PC=11111111 AR_Bus_PC_4=33333333 AR_Bus_Sel=10 AR_Output_Bus=55555555
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AR_Bus_Alu=ffffffff AR_Bus_PC=11111111 AR_Bus_PC_4=ffffffff AR_Bus_Sel=00 AR_Output_Bus=33333333
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AR_Bus_Alu=ffffffff AR_Bus_PC=11111111 AR_Bus_PC_4=ffffffff AR_Bus_Sel=00 AR_Output_Bus=ffffffff
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          5 tests run
--Tests Completed--