www.pudn.com > DDSforsinandcos.rar > mux6.vhd

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity mux6 is 
port( 
    s :in std_logic_vector(2 downto 0); 
    muxin1,muxin2,muxin3,muxin4 : in std_logic_vector(6 downto 0); 
    y1,y2,y3,y4 : out std_logic 
); 
end mux6; 
architecture behave of mux6 is 
begin 
  process(s,muxin1,muxin2,muxin3,muxin4) 
  begin 
    if s="000" then 
      y1<=muxin1(0);y2<=muxin2(0);y3<=muxin3(0);y4<=muxin4(0); 
     elsif s="001"then 
      y1<=muxin1(1);y2<=muxin2(1);y3<=muxin3(1);y4<=muxin4(1); 
      elsif s="010"then 
      y1<=muxin1(2);y2<=muxin2(2);y3<=muxin3(2);y4<=muxin4(2); 
       elsif s="011"then 
      y1<=muxin1(3);y2<=muxin2(3);y3<=muxin3(3);y4<=muxin4(3); 
       elsif s="100"then 
      y1<=muxin1(4);y2<=muxin2(4);y3<=muxin3(4);y4<=muxin4(4);  
       elsif s="101"then  
      y1<=muxin1(5);y2<=muxin2(5);y3<=muxin3(5);y4<=muxin4(5); 
        else  
      y1<=muxin1(6);y2<=muxin2(6);y3<=muxin3(6);y4<=muxin4(6); 
    end if; 
  end process; 
end behave;