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library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity judgedate is 
  port( 
     cindate :in std_logic_vector(8 downto 0); 
     coutdate : out std_logic_vector(7 downto 0) 
); 
end judgedate; 
architecture behave of judgedate is 
  begin  
process(cindate) 
   begin 
   if(cindate(8)='1') then 
      coutdate<=not cindate(7 downto 0); 
   else 
     coutdate<=cindate(7 downto 0); 
  end if; 
end process; 
end behave;