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library ieee; 
use ieee.std_logic_1164.all; 
entity shifter is 
port  
(data :in std_logic_vector(7 downto 0); 
 reset,clk :in std_logic; 
 qout :buffer std_logic_vector(7 downto 0) 
); 
end shifter; 
 
architecture behave of shifter is 
signal q1,q0 :std_logic; 
begin  
 process(clk) 
  begin 
   if(clk'event and clk='1')then 
    if(reset='1')then 
     qout<=(others=>'0')  ;  --ͬ²½ÇàÁã 
     else 
      qout<=data; 
    end if; 
   end if; 
  end process; 
end behave;