www.pudn.com > DDSforsinandcos.rar > conclk.vhd

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity conclk is port 
( 
   clk : in std_logic; 
   clr :in std_logic; 
   s   :buffer std_logic_vector(2 downto 0) 
); 
end conclk; 
architecture behave of conclk is 
  begin  
   process(clk,clr) 
  begin 
     if(clr='1')then 
      s<="000"; 
     elsif(clk'event and clk='1')then 
       if(s="110")then 
          s<="000"; 
       else s<=s+1; 
      end if; 
end if; 
     end process; 
end behave;