www.pudn.com > DDSforsinandcos.rar > 2fenpin.vhd

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity fen2pin is port 
( 
   clk :in std_logic; 
   sel :out std_logic; 
   nsel: out std_logic 
); 
end fen2pin; 
architecture behave of fen2pin is 
   signal  half :std_logic; 
 begin  
   process(clk) 
      begin 
     if(clk'event and clk='1')then 
      half<= not half; 
      end if; 
     end process; 
   sel<=half; 
   nsel<=not half; 
end behave;