www.pudn.com > Verilog-master.zip > ad_urat.hier_info, change:2016-04-28,size:22816b


|ad_urat
clk => clk.IN3
rst => rst.IN2
ad_busy => ad_busy.IN1
datain[0] => datain[0].IN1
datain[1] => datain[1].IN1
datain[2] => datain[2].IN1
datain[3] => datain[3].IN1
datain[4] => datain[4].IN1
datain[5] => datain[5].IN1
datain[6] => datain[6].IN1
datain[7] => datain[7].IN1
datain[8] => datain[8].IN1
datain[9] => datain[9].IN1
datain[10] => datain[10].IN1
datain[11] => datain[11].IN1
datain[12] => datain[12].IN1
datain[13] => datain[13].IN1
datain[14] => datain[14].IN1
datain[15] => datain[15].IN1
os[0] << ad7606:ad7606.os
os[1] << ad7606:ad7606.os
os[2] << ad7606:ad7606.os
rd << ad7606:ad7606.rd
cs << ad7606:ad7606.cs
range << ad7606:ad7606.range
convst[0] << ad7606:ad7606.convst
convst[1] << ad7606:ad7606.convst
ad_rst << ad7606:ad7606.ad_rst
TxD << UART_TX:UART_TX.TxD


|ad_urat|UART_TX:UART_TX
clk => TxD~reg0.CLK
clk => TxD_dataReg[0].CLK
clk => TxD_dataReg[1].CLK
clk => TxD_dataReg[2].CLK
clk => TxD_dataReg[3].CLK
clk => TxD_dataReg[4].CLK
clk => TxD_dataReg[5].CLK
clk => TxD_dataReg[6].CLK
clk => TxD_dataReg[7].CLK
clk => BaudGeneratorAcc[0].CLK
clk => BaudGeneratorAcc[1].CLK
clk => BaudGeneratorAcc[2].CLK
clk => BaudGeneratorAcc[3].CLK
clk => BaudGeneratorAcc[4].CLK
clk => BaudGeneratorAcc[5].CLK
clk => BaudGeneratorAcc[6].CLK
clk => BaudGeneratorAcc[7].CLK
clk => BaudGeneratorAcc[8].CLK
clk => BaudGeneratorAcc[9].CLK
clk => BaudGeneratorAcc[10].CLK
clk => BaudGeneratorAcc[11].CLK
clk => BaudGeneratorAcc[12].CLK
clk => BaudGeneratorAcc[13].CLK
clk => BaudGeneratorAcc[14].CLK
clk => BaudGeneratorAcc[15].CLK
clk => BaudGeneratorAcc[16].CLK
clk => state~12.DATAIN
rst => BaudGeneratorAcc[0].ACLR
rst => BaudGeneratorAcc[1].ACLR
rst => BaudGeneratorAcc[2].ACLR
rst => BaudGeneratorAcc[3].ACLR
rst => BaudGeneratorAcc[4].ACLR
rst => BaudGeneratorAcc[5].ACLR
rst => BaudGeneratorAcc[6].ACLR
rst => BaudGeneratorAcc[7].ACLR
rst => BaudGeneratorAcc[8].ACLR
rst => BaudGeneratorAcc[9].ACLR
rst => BaudGeneratorAcc[10].ACLR
rst => BaudGeneratorAcc[11].ACLR
rst => BaudGeneratorAcc[12].ACLR
rst => BaudGeneratorAcc[13].ACLR
rst => BaudGeneratorAcc[14].ACLR
rst => BaudGeneratorAcc[15].ACLR
rst => BaudGeneratorAcc[16].ACLR
rst => TxD~reg0.PRESET
rst => TxD_dataReg[0].ACLR
rst => TxD_dataReg[1].ACLR
rst => TxD_dataReg[2].ACLR
rst => TxD_dataReg[3].ACLR
rst => TxD_dataReg[4].ACLR
rst => TxD_dataReg[5].ACLR
rst => TxD_dataReg[6].ACLR
rst => TxD_dataReg[7].ACLR
rst => state~14.DATAIN
TxD_start => always1.IN1
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_start => state.OUTPUTSELECT
TxD_data[0] => TxD_dataReg[0].DATAIN
TxD_data[1] => TxD_dataReg[1].DATAIN
TxD_data[2] => TxD_dataReg[2].DATAIN
TxD_data[3] => TxD_dataReg[3].DATAIN
TxD_data[4] => TxD_dataReg[4].DATAIN
TxD_data[5] => TxD_dataReg[5].DATAIN
TxD_data[6] => TxD_dataReg[6].DATAIN
TxD_data[7] => TxD_dataReg[7].DATAIN
TxD <= TxD~reg0.DB_MAX_OUTPUT_PORT_TYPE
TxD_busy <= TxD_ready.DB_MAX_OUTPUT_PORT_TYPE


|ad_urat|ad7606:ad7606
clk => dataout[0]~reg0.CLK
clk => dataout[1]~reg0.CLK
clk => dataout[2]~reg0.CLK
clk => dataout[3]~reg0.CLK
clk => dataout[4]~reg0.CLK
clk => dataout[5]~reg0.CLK
clk => dataout[6]~reg0.CLK
clk => dataout[7]~reg0.CLK
clk => dataout[8]~reg0.CLK
clk => dataout[9]~reg0.CLK
clk => dataout[10]~reg0.CLK
clk => dataout[11]~reg0.CLK
clk => dataout[12]~reg0.CLK
clk => dataout[13]~reg0.CLK
clk => dataout[14]~reg0.CLK
clk => dataout[15]~reg0.CLK
clk => channel[0].CLK
clk => channel[1].CLK
clk => channel[2].CLK
clk => channel[3].CLK
clk => status~reg0.CLK
clk => rd~reg0.CLK
clk => cs~reg0.CLK
clk => convst_low_cnt[0].CLK
clk => convst_low_cnt[1].CLK
clk => convst_low_cnt[2].CLK
clk => convst_low_cnt[3].CLK
clk => convst_low_cnt[4].CLK
clk => convst_low_cnt[5].CLK
clk => convst[0]~reg0.CLK
clk => convst[1]~reg0.CLK
clk => ad_rst~reg0.CLK
clk => cnt500us[0].CLK
clk => cnt500us[1].CLK
clk => cnt500us[2].CLK
clk => cnt500us[3].CLK
clk => cnt500us[4].CLK
clk => cnt500us[5].CLK
clk => cnt500us[6].CLK
clk => cnt500us[7].CLK
clk => cnt500us[8].CLK
clk => cnt500us[9].CLK
clk => cnt500us[10].CLK
clk => cnt500us[11].CLK
clk => cnt500us[12].CLK
clk => cnt500us[13].CLK
clk => cnt500us[14].CLK
clk => cnt500us[15].CLK
clk => state~1.DATAIN
rst => ad_rst~reg0.PRESET
rst => cnt500us[0].ACLR
rst => cnt500us[1].ACLR
rst => cnt500us[2].ACLR
rst => cnt500us[3].ACLR
rst => cnt500us[4].ACLR
rst => cnt500us[5].ACLR
rst => cnt500us[6].ACLR
rst => cnt500us[7].ACLR
rst => cnt500us[8].ACLR
rst => cnt500us[9].ACLR
rst => cnt500us[10].ACLR
rst => cnt500us[11].ACLR
rst => cnt500us[12].ACLR
rst => cnt500us[13].ACLR
rst => cnt500us[14].ACLR
rst => cnt500us[15].ACLR
rst => state~3.DATAIN
rst => dataout[0]~reg0.ENA
rst => convst[1]~reg0.ENA
rst => convst[0]~reg0.ENA
rst => convst_low_cnt[5].ENA
rst => convst_low_cnt[4].ENA
rst => convst_low_cnt[3].ENA
rst => convst_low_cnt[2].ENA
rst => convst_low_cnt[1].ENA
rst => convst_low_cnt[0].ENA
rst => cs~reg0.ENA
rst => rd~reg0.ENA
rst => status~reg0.ENA
rst => channel[3].ENA
rst => channel[2].ENA
rst => channel[1].ENA
rst => channel[0].ENA
rst => dataout[15]~reg0.ENA
rst => dataout[14]~reg0.ENA
rst => dataout[13]~reg0.ENA
rst => dataout[12]~reg0.ENA
rst => dataout[11]~reg0.ENA
rst => dataout[10]~reg0.ENA
rst => dataout[9]~reg0.ENA
rst => dataout[8]~reg0.ENA
rst => dataout[7]~reg0.ENA
rst => dataout[6]~reg0.ENA
rst => dataout[5]~reg0.ENA
rst => dataout[4]~reg0.ENA
rst => dataout[3]~reg0.ENA
rst => dataout[2]~reg0.ENA
rst => dataout[1]~reg0.ENA
ram_busy => state.OUTPUTSELECT
ram_busy => state.OUTPUTSELECT
ram_busy => Selector14.IN3
ad_busy => Selector12.IN3
ad_busy => Selector16.IN1
datain[0] => dataout.DATAB
datain[1] => dataout.DATAB
datain[2] => dataout.DATAB
datain[3] => dataout.DATAB
datain[4] => dataout.DATAB
datain[5] => dataout.DATAB
datain[6] => dataout.DATAB
datain[7] => dataout.DATAB
datain[8] => dataout.DATAB
datain[9] => dataout.DATAB
datain[10] => dataout.DATAB
datain[11] => dataout.DATAB
datain[12] => dataout.DATAB
datain[13] => dataout.DATAB
datain[14] => dataout.DATAB
datain[15] => dataout.DATAB
os[0] <= <GND>
os[1] <= <GND>
os[2] <= <GND>
rd <= rd~reg0.DB_MAX_OUTPUT_PORT_TYPE
cs <= cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
range <= <GND>
convst[0] <= convst[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
convst[1] <= convst[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_rst <= ad_rst~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[0] <= dataout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= dataout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= dataout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= dataout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= dataout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= dataout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[6] <= dataout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[7] <= dataout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[8] <= dataout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[9] <= dataout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[10] <= dataout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[11] <= dataout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[12] <= dataout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[13] <= dataout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[14] <= dataout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout[15] <= dataout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
status <= status~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ad_urat|RAM:RAM
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
address[8] => address[8].IN1
address[9] => address[9].IN1
address[10] => address[10].IN1
address[11] => address[11].IN1
address[12] => address[12].IN1
clock => clock.IN1
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
data[8] => data[8].IN1
data[9] => data[9].IN1
data[10] => data[10].IN1
data[11] => data[11].IN1
data[12] => data[12].IN1
data[13] => data[13].IN1
data[14] => data[14].IN1
data[15] => data[15].IN1
wren => wren.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a
q[14] <= altsyncram:altsyncram_component.q_a
q[15] <= altsyncram:altsyncram_component.q_a


|ad_urat|RAM:RAM|altsyncram:altsyncram_component
wren_a => altsyncram_qda1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_qda1:auto_generated.data_a[0]
data_a[1] => altsyncram_qda1:auto_generated.data_a[1]
data_a[2] => altsyncram_qda1:auto_generated.data_a[2]
data_a[3] => altsyncram_qda1:auto_generated.data_a[3]
data_a[4] => altsyncram_qda1:auto_generated.data_a[4]
data_a[5] => altsyncram_qda1:auto_generated.data_a[5]
data_a[6] => altsyncram_qda1:auto_generated.data_a[6]
data_a[7] => altsyncram_qda1:auto_generated.data_a[7]
data_a[8] => altsyncram_qda1:auto_generated.data_a[8]
data_a[9] => altsyncram_qda1:auto_generated.data_a[9]
data_a[10] => altsyncram_qda1:auto_generated.data_a[10]
data_a[11] => altsyncram_qda1:auto_generated.data_a[11]
data_a[12] => altsyncram_qda1:auto_generated.data_a[12]
data_a[13] => altsyncram_qda1:auto_generated.data_a[13]
data_a[14] => altsyncram_qda1:auto_generated.data_a[14]
data_a[15] => altsyncram_qda1:auto_generated.data_a[15]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_qda1:auto_generated.address_a[0]
address_a[1] => altsyncram_qda1:auto_generated.address_a[1]
address_a[2] => altsyncram_qda1:auto_generated.address_a[2]
address_a[3] => altsyncram_qda1:auto_generated.address_a[3]
address_a[4] => altsyncram_qda1:auto_generated.address_a[4]
address_a[5] => altsyncram_qda1:auto_generated.address_a[5]
address_a[6] => altsyncram_qda1:auto_generated.address_a[6]
address_a[7] => altsyncram_qda1:auto_generated.address_a[7]
address_a[8] => altsyncram_qda1:auto_generated.address_a[8]
address_a[9] => altsyncram_qda1:auto_generated.address_a[9]
address_a[10] => altsyncram_qda1:auto_generated.address_a[10]
address_a[11] => altsyncram_qda1:auto_generated.address_a[11]
address_a[12] => altsyncram_qda1:auto_generated.address_a[12]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_qda1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_qda1:auto_generated.q_a[0]
q_a[1] <= altsyncram_qda1:auto_generated.q_a[1]
q_a[2] <= altsyncram_qda1:auto_generated.q_a[2]
q_a[3] <= altsyncram_qda1:auto_generated.q_a[3]
q_a[4] <= altsyncram_qda1:auto_generated.q_a[4]
q_a[5] <= altsyncram_qda1:auto_generated.q_a[5]
q_a[6] <= altsyncram_qda1:auto_generated.q_a[6]
q_a[7] <= altsyncram_qda1:auto_generated.q_a[7]
q_a[8] <= altsyncram_qda1:auto_generated.q_a[8]
q_a[9] <= altsyncram_qda1:auto_generated.q_a[9]
q_a[10] <= altsyncram_qda1:auto_generated.q_a[10]
q_a[11] <= altsyncram_qda1:auto_generated.q_a[11]
q_a[12] <= altsyncram_qda1:auto_generated.q_a[12]
q_a[13] <= altsyncram_qda1:auto_generated.q_a[13]
q_a[14] <= altsyncram_qda1:auto_generated.q_a[14]
q_a[15] <= altsyncram_qda1:auto_generated.q_a[15]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|ad_urat|RAM:RAM|altsyncram:altsyncram_component|altsyncram_qda1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[12] => ram_block1a0.PORTAADDR12
address_a[12] => ram_block1a1.PORTAADDR12
address_a[12] => ram_block1a2.PORTAADDR12
address_a[12] => ram_block1a3.PORTAADDR12
address_a[12] => ram_block1a4.PORTAADDR12
address_a[12] => ram_block1a5.PORTAADDR12
address_a[12] => ram_block1a6.PORTAADDR12
address_a[12] => ram_block1a7.PORTAADDR12
address_a[12] => ram_block1a8.PORTAADDR12
address_a[12] => ram_block1a9.PORTAADDR12
address_a[12] => ram_block1a10.PORTAADDR12
address_a[12] => ram_block1a11.PORTAADDR12
address_a[12] => ram_block1a12.PORTAADDR12
address_a[12] => ram_block1a13.PORTAADDR12
address_a[12] => ram_block1a14.PORTAADDR12
address_a[12] => ram_block1a15.PORTAADDR12
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE