www.pudn.com > Verilog-master.zip > ad7606.v, change:2016-04-28,size:3677b


module ad7606
(clk,
rst,
ram_busy,
ad_busy,
datain,
os,
rd,
cs,
range,
convst,
ad_rst,
dataout,
status
);
input	clk;
input rst;
input ram_busy;
input ad_busy;
input [15:0] datain;  //AD骞惰鏁版嵁杈撳叆
output [2:0] os;  //杩囬噰鏍锋帶鍒
output rd;  //閲囩敤鏁版嵁骞惰妯″紡锛宑s涓巖d鐙珛鑴夊啿锛屽綋cs涓轰綆锛宺d涓嬮檷娌挎椂杩涜AD鏁版嵁骞惰璇诲彇
output cs;  //鐗囬€変俊鍙风瀛
output range;  //杈撳叆鐢靛帇閫夋嫨锛屽綋涓洪珮鐢靛钩鏃讹紝杈撳叆涓烘璐0V锛屽綋涓轰綆鐢靛钩鏃讹紝杈撳叆涓烘璐v
output [1:0] convst;   //AD杞崲浣胯兘锛屼笂鍗囨部AD寮€濮嬭浆鎹
output ad_rst;
output [15:0] dataout;  //璇诲彇鐨6浣岮D杈撳嚭鏁版嵁
output status;  //璇籄D鐘舵€佺粨鏉熸爣蹇楋紝褰撴暟鎹鍙栧畬鎴愭椂锛屽彉涓洪珮鐢靛钩


//reg [7:0] cnt5us;
reg [15:0] cnt500us;
reg delay20ns;
reg delayflag;
reg [5:0] convst_low_cnt;
reg [3:0] state;
reg cs;
reg rd;
reg [1:0] convst;
reg ad_rst;
reg [15:0] dataout;
reg status;
reg [5:0] num;
reg [2:0] cnt;
reg [3:0] channel;

parameter idle=4'd0;
parameter state1=4'd1;
parameter state2=4'd2;
//parameter state2=4'd2;
parameter state3=4'd3;
parameter state4=4'd4;
parameter state5=4'd5;
parameter display=4'd6;
parameter statex=4'd7;
parameter statex1=4'd8;


always@(posedge clk or negedge rst)
begin
if(~rst)
 begin
	cnt500us <= 0;
 end
else
 begin 
 if(cnt500us<16'd25000)
	cnt500us <= cnt500us+1;
 else
	begin
	  cnt500us <= 0;
	end
 end
end


always@(posedge clk or negedge rst)
begin
if(rst == 0)
begin
	ad_rst <= 1;
	state <= idle;
end
else
begin
case(state)
	idle:
	begin
	   ad_rst <= 0; 
		convst <= 2'b11;
		convst_low_cnt <= 6'd0;
		cs <= 1;
		rd <= 1;
		status <= 0;	
		state <= state1;	
		channel<=0;
	end
	state1:
	begin
		ad_rst <= 0;
		convst <= 2'b00;
		cs <= 1;
		rd <= 1;
		status <= 0;
		if(convst_low_cnt == 6'd1)
		begin
			convst_low_cnt<=0;
			state <= state2;
		end
		else
		begin
			state <= state1;
		end
		convst_low_cnt <= convst_low_cnt+1;
	end
	state2:
	begin
		ad_rst <= 0;
		convst <= 2'b11;
		convst_low_cnt <= 6'd0;
		cs <= 1;
		rd <= 1;
		status <= 0;
		state <= state3;
	end
	state3:
		begin
			if(ad_busy == 1)
				begin
					state <= state3;
				end
			else
				begin
					state<=statex;
				end 
		end 
	statex:
		begin 
			convst_low_cnt<=0;
			ad_rst <= 0;
			convst <= 2'b11;
			cs <= 0;
			rd <= 0;
			status <= 0;
			dataout <= datain;
			channel<=channel+1;
			state <= state4;
		end 
	state4:
		begin 
			cs<=1;
			rd<=1;
			ad_rst <= 0;
			convst <= 2'b11;
//			convst_low_cnt <= 6'd0;
			status <= 1;
			if(convst_low_cnt<=1)
			begin 
				state<=state4;
			end 
			else 
			begin 
				convst_low_cnt<=0;
				state<=state5;
			end 
			convst_low_cnt<=convst_low_cnt+1;
		end 
	state5:
		begin
			if(ram_busy==1)
			begin 
				ad_rst <= 0;
				convst <= 2'b11;
				convst_low_cnt <= 6'd0;
				cs <= 1;
				rd <= 1;
				status <= 0;
				state <= state5;
			end 
			else 
			begin 
				ad_rst <= 0;
				convst <= 2'b11;
				convst_low_cnt <= 6'd0;
				cs <= 1;
				rd <= 1;
				status <= 0;
				if(channel <= 4'd3)       // 0~7分别对应采样通道数1~8  ,任何情况下,最后一个通道的读数毛刺很大
					begin
						state <= statex;
					end
				else
					begin
						state <= display;
					end
			end 	
		end 
	display:
	begin 
			if(cnt500us == 16'd25000)
				  begin
						state <= idle;
				  end
		     else
			     begin
				      state <=display;
			     end
	end
	default:
		state <= idle;
endcase
end
end

assign os = 3'd0;
assign range = 1'b0;
endmodule