www.pudn.com > BLDC_Sensorless_FOC.rar > bdrv_defines.h, change:2015-08-17,size:3616b


/*sha256=071E50386A53389580F34FD8EAF7648B0F586585B6EBBF83EF74622ED7C715A7*/ 
/** 
 * @cond 
 *********************************************************************************************************************** 
 * 
 * Copyright (c) 2015, Infineon Technologies AG 
 * All rights reserved. 
 * 
 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
 * following conditions are met: 
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 *   Redistributions of source code must retain the above copyright notice, this list of conditions and the  following 
 *   disclaimer. 
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 *   Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the 
 *   following disclaimer in the documentation and/or other materials provided with the distribution. 
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 *   Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 
 *   products derived from this software without specific prior written permission. 
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
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 **********************************************************************************************************************/ 
 
/*------------------------------------------------------------------------------ 
IFXConfigWizard output file 
created on:Mo Aug 17 13:48:35 2015 
------------------------------------------------------------------------------*/ 
 
#ifndef _BDRV_DEFINES_H 
#define _BDRV_DEFINES_H 
 
#ifndef IFXConfigWizard_Version 
  #define IFXConfigWizard_Version 1.8.2 
#endif 
 
/*BDRV_CP_CLK_CTRL: (1<<15)|(10<<8)|22|(2<<13)*/ 
#ifndef BDRV_CP_CLK_CTRL 
  #define BDRV_CP_CLK_CTRL (0xCA16u) 
#endif 
 
/*BDRV_CP_CTRL_STS: 1|(3<<26)|(0<<24)|(0<<22)|(0<<20)|(0<<18)|(0<<16)|(0<<8)|(0\ 
<<25)*/ 
#ifndef BDRV_CP_CTRL_STS 
  #define BDRV_CP_CTRL_STS (0xC000001u) 
#endif 
 
/*BDRV_CTRL3: (2<<16)|(0<<24)|(1<<6)|17|(1<<14)|(17<<8)|(0<<7)|(0<<15)|(0<<26)*/ 
#ifndef BDRV_CTRL3 
  #define BDRV_CTRL3 (0x25151u) 
#endif 
 
#ifndef BDRV_EFF_CRG_CURR 
  #define BDRV_EFF_CRG_CURR 179.922 
#endif 
 
#ifndef BDRV_EFF_DISCRG_CURR 
  #define BDRV_EFF_DISCRG_CURR 179.922 
#endif 
 
/*BDRV_OFF_SEQ: (0<<27)|(0<<24)|(0<<19)|(0<<16)|(0<<11)|(0<<8)|(0<<3)|0*/ 
#ifndef BDRV_OFF_SEQ 
  #define BDRV_OFF_SEQ (0x0u) 
#endif 
 
/*BDRV_ON_SEQ: (0<<27)|(0<<24)|(0<<19)|(0<<16)|(0<<11)|(0<<8)|(0<<3)|0*/ 
#ifndef BDRV_ON_SEQ 
  #define BDRV_ON_SEQ (0x0u) 
#endif 
 
/*BDRV_TRIM_DRVx: (0<<24)|(1<<10)|(1<<11)|(1<<12)|(1<<18)|(1<<19)|(1<<20)|(1<<1\ 
3)|(1<<14)|(1<<15)|(1<<21)|(1<<22)|(1<<23)|(1<<16)|(1<<8)|1*/ 
#ifndef BDRV_TRIM_DRVx 
  #define BDRV_TRIM_DRVx (0xFDFD01u) 
#endif 
 
/*MF_BEMFC_CTRL_STS: 0|(0<<8)|(0<<12)|(0<<5)|(0<<4)|(0<<3)*/ 
#ifndef MF_BEMFC_CTRL_STS 
  #define MF_BEMFC_CTRL_STS (0x0u) 
#endif 
 
/*MF_TRIM_BEMFx: (0<<8)|4*/ 
#ifndef MF_TRIM_BEMFx 
  #define MF_TRIM_BEMFx (0x4u) 
#endif 
 
 
#endif