www.pudn.com > BLDC_Sensorless_FOC.rar > adc1_defines.h, change:2015-08-17,size:4654b


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/** 
 * @cond 
 *********************************************************************************************************************** 
 * 
 * Copyright (c) 2015, Infineon Technologies AG 
 * All rights reserved. 
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 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 
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 *   Redistributions of source code must retain the above copyright notice, this list of conditions and the  following 
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/*------------------------------------------------------------------------------ 
IFXConfigWizard output file 
created on:Mo Aug 17 13:48:35 2015 
------------------------------------------------------------------------------*/ 
 
#ifndef _ADC1_DEFINES_H 
#define _ADC1_DEFINES_H 
 
#ifndef IFXConfigWizard_Version 
  #define IFXConfigWizard_Version 1.8.2 
#endif 
 
/*ADC1_CHX_EIM: (0<<16)|0|(0<<4)*/ 
#ifndef ADC1_CHX_EIM 
  #define ADC1_CHX_EIM (0x0u) 
#endif 
 
#ifndef ADC1_CLK 
  #define ADC1_CLK 20 
#endif 
 
/*ADC1_DWSEL: 0|(0<<1)|(0<<2)|(0<<3)|(0<<4)|(0<<5)|(0<<6)*/ 
#ifndef ADC1_DWSEL 
  #define ADC1_DWSEL (0x0u) 
#endif 
 
/*ADC1_ESM: (1<<16)|0|(1<<1)|(0<<2)|(0<<3)|(0<<4)|(0<<5)|(0<<6)*/ 
#ifndef ADC1_ESM 
  #define ADC1_ESM (0x10002u) 
#endif 
 
/*ADC1_GLOBCTR: (3<<8)|1*/ 
#ifndef ADC1_GLOBCTR 
  #define ADC1_GLOBCTR (0x301u) 
#endif 
 
/*ADC1_IE: 0|(0<<1)|(0<<2)|(0<<3)|(0<<4)|(0<<5)|(0<<6)|(0<<8)|(1<<9)*/ 
#ifndef ADC1_IE 
  #define ADC1_IE (0x200u) 
#endif 
 
/*ADC1_RES0: (0<<16)*/ 
#ifndef ADC1_RES0 
  #define ADC1_RES0 (0x0u) 
#endif 
 
/*ADC1_RES1: (0<<16)*/ 
#ifndef ADC1_RES1 
  #define ADC1_RES1 (0x0u) 
#endif 
 
/*ADC1_RES2: (0<<16)*/ 
#ifndef ADC1_RES2 
  #define ADC1_RES2 (0x0u) 
#endif 
 
/*ADC1_RES3: (0<<16)*/ 
#ifndef ADC1_RES3 
  #define ADC1_RES3 (0x0u) 
#endif 
 
/*ADC1_RES4: (0<<16)*/ 
#ifndef ADC1_RES4 
  #define ADC1_RES4 (0x0u) 
#endif 
 
/*ADC1_RES5: (0<<16)*/ 
#ifndef ADC1_RES5 
  #define ADC1_RES5 (0x0u) 
#endif 
 
/*ADC1_RES6: (0<<16)*/ 
#ifndef ADC1_RES6 
  #define ADC1_RES6 (0x0u) 
#endif 
 
/*ADC1_RES_EIM: (0<<16)*/ 
#ifndef ADC1_RES_EIM 
  #define ADC1_RES_EIM (0x0u) 
#endif 
 
/*ADC1_SQ1_4: 0|(0<<1)|(0<<2)|(0<<3)|(1<<4)|(0<<5)|(0<<6)|(0<<8)|(0<<9)|(0<<10)\ 
|(0<<11)|(0<<12)|(0<<13)|(0<<14)|(0<<16)|(0<<17)|(0<<18)|(0<<19)|(0<<20)|(0<<21\ 
)|(0<<22)|(0<<24)|(0<<25)|(0<<26)|(0<<27)|(0<<28)|(0<<29)|(0<<30)*/ 
#ifndef ADC1_SQ1_4 
  #define ADC1_SQ1_4 (0x10u) 
#endif 
 
/*ADC1_SQ5_8: 0|(0<<1)|(0<<2)|(0<<3)|(0<<4)|(0<<5)|(0<<6)|(0<<8)|(0<<9)|(0<<10)\ 
|(0<<11)|(0<<12)|(0<<13)|(0<<14)|(0<<16)|(0<<17)|(0<<18)|(0<<19)|(0<<20)|(0<<21\ 
)|(0<<22)|(0<<24)|(0<<25)|(0<<26)|(0<<27)|(0<<28)|(0<<29)|(0<<30)*/ 
#ifndef ADC1_SQ5_8 
  #define ADC1_SQ5_8 (0x0u) 
#endif 
 
/*ADC1_SQ_FB: (1<<8)*/ 
#ifndef ADC1_SQ_FB 
  #define ADC1_SQ_FB (0x100u) 
#endif 
 
/*ADC1_STC_0_3: 0|(10<<8)|(0<<16)|(0<<24)*/ 
#ifndef ADC1_STC_0_3 
  #define ADC1_STC_0_3 (0xA00u) 
#endif 
 
/*ADC1_STC_4_7: 20|(0<<8)|(0<<16)*/ 
#ifndef ADC1_STC_4_7 
  #define ADC1_STC_4_7 (0x14u) 
#endif 
 
/*MF_REF2_CTRL: 1*/ 
#ifndef MF_REF2_CTRL 
  #define MF_REF2_CTRL (0x1u) 
#endif 
 
/*MF_VMON_SEN_CTRL: 0|(0<<4)|(0<<5)*/ 
#ifndef MF_VMON_SEN_CTRL 
  #define MF_VMON_SEN_CTRL (0x0u) 
#endif 
 
 
#endif