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--lpm_counter DEVICE_FAMILY="Stratix" lpm_direction="UP" lpm_width=5 aclr clk_en clock q 
--VERSION_BEGIN 4.2 cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_counter 2004:10:25:23:03:40:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ  VERSION_END 
 
 
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--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted), 
--  support information,  device programming or simulation file,  and any other 
--  associated  documentation or information  provided by  Altera  or a partner 
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any 
--  other  use  of such  megafunction  design,  netlist,  support  information, 
--  device programming or simulation file,  or any other  related documentation 
--  or information  is prohibited  for  any  other purpose,  including, but not 
--  limited to  modification,  reverse engineering,  de-compiling, or use  with 
--  any other  silicon devices,  unless such use is  explicitly  licensed under 
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--  intellectual property,  including patents,  copyrights,  trademarks,  trade 
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist, 
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FUNCTION stratix_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload) 
WITH ( 	cin_used,	lut_mask,	operation_mode,	output_mode,	register_cascade_mode,	sum_lutc_input,	synch_mode)  
RETURNS ( combout, cout, regout); 
 
--synthesis_resources = lut 5  
SUBDESIGN cntr_tv7 
(  
	aclr	:	input; 
	clk_en	:	input; 
	clock	:	input; 
	cout	:	output; 
	q[4..0]	:	output; 
)  
VARIABLE  
	counter_cella0 : stratix_lcell 
		WITH ( 
			cin_used = "false", 
			lut_mask = "11AA", 
			operation_mode = "arithmetic", 
			synch_mode = "on" 
		); 
	counter_cella1 : stratix_lcell 
		WITH ( 
			cin_used = "true", 
			lut_mask = "12A0", 
			operation_mode = "arithmetic", 
			sum_lutc_input = "cin", 
			synch_mode = "on" 
		); 
	counter_cella2 : stratix_lcell 
		WITH ( 
			cin_used = "true", 
			lut_mask = "12A0", 
			operation_mode = "arithmetic", 
			sum_lutc_input = "cin", 
			synch_mode = "on" 
		); 
	counter_cella3 : stratix_lcell 
		WITH ( 
			cin_used = "true", 
			lut_mask = "12A0", 
			operation_mode = "arithmetic", 
			sum_lutc_input = "cin", 
			synch_mode = "on" 
		); 
	counter_cella4 : stratix_lcell 
		WITH ( 
			cin_used = "true", 
			lut_mask = "12A0", 
			operation_mode = "arithmetic", 
			sum_lutc_input = "cin", 
			synch_mode = "on" 
		); 
	a_val[4..0]	: WIRE; 
	aclr_actual	: WIRE; 
	aset_node	: WIRE; 
	data[4..0]	: NODE; 
	s_val[4..0]	: WIRE; 
	safe_q[4..0]	: WIRE; 
	sclr	: NODE; 
	sload	: NODE; 
	sset_node	: WIRE; 
	time_to_clear	: WIRE; 
	updownDir	: WIRE; 
 
BEGIN  
	counter_cella[4..0].aclr = aclr_actual; 
	counter_cella[4..0].aload = B"00000"; 
	counter_cella[1].cin = counter_cella[0].cout; 
	counter_cella[2].cin = counter_cella[1].cout; 
	counter_cella[3].cin = counter_cella[2].cout; 
	counter_cella[4].cin = counter_cella[3].cout; 
	counter_cella[4..0].clk = clock; 
	counter_cella[4..0].dataa = safe_q[]; 
	counter_cella[4..0].datab = B"00000"; 
	counter_cella[4..0].datac = data[]; 
	counter_cella[4..0].ena = clk_en; 
	counter_cella[4..0].sclr = sclr; 
	counter_cella[4..0].sload = sload; 
	a_val[] = B"11111"; 
	aclr_actual = aclr; 
	aset_node = B"0"; 
	cout = counter_cella[4].cout; 
	data[] = GND; 
	q[] = safe_q[]; 
	s_val[] = B"11111"; 
	safe_q[] = counter_cella[4..0].regout; 
	sclr = GND; 
	sload = GND; 
	sset_node = B"0"; 
	time_to_clear = B"0"; 
	updownDir = B"1"; 
END; 
--VALID FILE