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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" NUMWORDS_A=3 NUMWORDS_B=3 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" WIDTH_A=64 WIDTH_B=64 WIDTHAD_A=2 WIDTHAD_B=2 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a --VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END -- Copyright (C) 1988-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. PARAMETERS ( PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_DATA_WIDTH = 1, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_DATA_WIDTH = 1 ); FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe) WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, RAM_BLOCK_TYPE) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = ram_bits (auto) 192 SUBDESIGN altsyncram_df61 ( address_a[1..0] : input; address_b[1..0] : input; clock0 : input; clock1 : input; clocken1 : input; data_a[63..0] : input; q_b[63..0] : output; wren_a : input; ) VARIABLE ram_block1a0 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a1 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a2 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a3 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a4 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a5 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 5, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a6 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 6, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a7 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 7, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a8 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 8, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 8, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a9 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 9, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 9, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a10 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 10, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 10, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a11 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 11, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 11, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a12 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 12, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 12, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a13 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 13, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 13, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a14 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 14, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 14, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a15 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 15, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 15, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a16 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 16, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 16, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a17 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 17, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 17, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a18 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 18, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 18, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a19 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 19, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 19, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a20 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 20, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 20, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a21 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 21, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 21, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a22 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 22, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 22, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a23 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 23, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 23, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a24 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 24, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 24, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a25 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 25, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 25, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a26 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 26, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 26, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a27 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 27, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 27, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a28 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 28, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 28, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a29 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 29, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 29, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a30 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 30, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 30, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a31 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 31, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 31, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a32 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 32, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 32, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a33 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 33, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 33, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a34 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 34, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 34, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a35 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 35, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 35, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a36 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 36, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 36, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a37 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 37, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 37, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a38 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 38, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 38, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a39 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 39, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 39, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a40 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 40, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 40, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a41 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 41, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 41, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a42 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 42, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 42, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a43 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 43, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 43, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a44 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 44, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 44, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a45 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 45, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 45, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a46 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 46, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 46, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a47 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 47, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 47, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a48 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 48, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 48, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a49 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 49, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 49, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a50 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 50, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 50, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a51 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 51, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 51, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a52 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 52, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 52, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a53 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 53, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 53, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a54 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 54, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 54, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a55 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 55, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 55, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a56 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 56, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 56, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a57 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 57, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 57, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a58 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 58, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 58, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a59 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 59, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 59, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a60 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 60, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 60, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a61 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 61, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 61, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a62 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 62, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 62, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block1a63 : stratixii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 2, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 63, PORT_A_LAST_ADDRESS = 2, PORT_A_LOGICAL_RAM_DEPTH = 3, PORT_A_LOGICAL_RAM_WIDTH = 64, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 2, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_OUT_CLOCK = "none", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 63, PORT_B_LAST_ADDRESS = 2, PORT_B_LOGICAL_RAM_DEPTH = 3, PORT_B_LOGICAL_RAM_WIDTH = 64, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); address_a_wire[1..0] : WIRE; address_b_wire[1..0] : WIRE; BEGIN ram_block1a[63..0].clk0 = clock0; ram_block1a[63..0].clk1 = clock1; ram_block1a[63..0].ena0 = wren_a; ram_block1a[63..0].ena1 = clocken1; ram_block1a[0].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[1].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[2].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[3].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[4].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[5].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[6].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[7].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[8].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[9].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[10].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[11].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[12].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[13].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[14].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[15].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[16].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[17].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[18].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[19].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[20].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[21].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[22].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[23].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[24].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[25].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[26].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[27].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[28].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[29].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[30].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[31].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[32].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[33].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[34].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[35].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[36].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[37].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[38].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[39].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[40].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[41].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[42].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[43].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[44].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[45].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[46].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[47].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[48].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[49].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[50].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[51].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[52].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[53].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[54].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[55].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[56].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[57].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[58].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[59].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[60].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[61].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[62].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[63].portaaddr[] = ( address_a_wire[1..0]); ram_block1a[0].portadatain[] = ( data_a[0..0]); ram_block1a[1].portadatain[] = ( data_a[1..1]); ram_block1a[2].portadatain[] = ( data_a[2..2]); ram_block1a[3].portadatain[] = ( data_a[3..3]); ram_block1a[4].portadatain[] = ( data_a[4..4]); ram_block1a[5].portadatain[] = ( data_a[5..5]); ram_block1a[6].portadatain[] = ( data_a[6..6]); ram_block1a[7].portadatain[] = ( data_a[7..7]); ram_block1a[8].portadatain[] = ( data_a[8..8]); ram_block1a[9].portadatain[] = ( data_a[9..9]); ram_block1a[10].portadatain[] = ( data_a[10..10]); ram_block1a[11].portadatain[] = ( data_a[11..11]); ram_block1a[12].portadatain[] = ( data_a[12..12]); ram_block1a[13].portadatain[] = ( data_a[13..13]); ram_block1a[14].portadatain[] = ( data_a[14..14]); ram_block1a[15].portadatain[] = ( data_a[15..15]); ram_block1a[16].portadatain[] = ( data_a[16..16]); ram_block1a[17].portadatain[] = ( data_a[17..17]); ram_block1a[18].portadatain[] = ( data_a[18..18]); ram_block1a[19].portadatain[] = ( data_a[19..19]); ram_block1a[20].portadatain[] = ( data_a[20..20]); ram_block1a[21].portadatain[] = ( data_a[21..21]); ram_block1a[22].portadatain[] = ( data_a[22..22]); ram_block1a[23].portadatain[] = ( data_a[23..23]); ram_block1a[24].portadatain[] = ( data_a[24..24]); ram_block1a[25].portadatain[] = ( data_a[25..25]); ram_block1a[26].portadatain[] = ( data_a[26..26]); ram_block1a[27].portadatain[] = ( data_a[27..27]); ram_block1a[28].portadatain[] = ( data_a[28..28]); ram_block1a[29].portadatain[] = ( data_a[29..29]); ram_block1a[30].portadatain[] = ( data_a[30..30]); ram_block1a[31].portadatain[] = ( data_a[31..31]); ram_block1a[32].portadatain[] = ( data_a[32..32]); ram_block1a[33].portadatain[] = ( data_a[33..33]); ram_block1a[34].portadatain[] = ( data_a[34..34]); ram_block1a[35].portadatain[] = ( data_a[35..35]); ram_block1a[36].portadatain[] = ( data_a[36..36]); ram_block1a[37].portadatain[] = ( data_a[37..37]); ram_block1a[38].portadatain[] = ( data_a[38..38]); ram_block1a[39].portadatain[] = ( data_a[39..39]); ram_block1a[40].portadatain[] = ( data_a[40..40]); ram_block1a[41].portadatain[] = ( data_a[41..41]); ram_block1a[42].portadatain[] = ( data_a[42..42]); ram_block1a[43].portadatain[] = ( data_a[43..43]); ram_block1a[44].portadatain[] = ( data_a[44..44]); ram_block1a[45].portadatain[] = ( data_a[45..45]); ram_block1a[46].portadatain[] = ( data_a[46..46]); ram_block1a[47].portadatain[] = ( data_a[47..47]); ram_block1a[48].portadatain[] = ( data_a[48..48]); ram_block1a[49].portadatain[] = ( data_a[49..49]); ram_block1a[50].portadatain[] = ( data_a[50..50]); ram_block1a[51].portadatain[] = ( data_a[51..51]); ram_block1a[52].portadatain[] = ( data_a[52..52]); ram_block1a[53].portadatain[] = ( data_a[53..53]); ram_block1a[54].portadatain[] = ( data_a[54..54]); ram_block1a[55].portadatain[] = ( data_a[55..55]); ram_block1a[56].portadatain[] = ( data_a[56..56]); ram_block1a[57].portadatain[] = ( data_a[57..57]); ram_block1a[58].portadatain[] = ( data_a[58..58]); ram_block1a[59].portadatain[] = ( data_a[59..59]); ram_block1a[60].portadatain[] = ( data_a[60..60]); ram_block1a[61].portadatain[] = ( data_a[61..61]); ram_block1a[62].portadatain[] = ( data_a[62..62]); ram_block1a[63].portadatain[] = ( data_a[63..63]); ram_block1a[63..0].portawe = B"1111111111111111111111111111111111111111111111111111111111111111"; ram_block1a[0].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[1].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[2].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[3].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[4].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[5].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[6].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[7].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[8].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[9].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[10].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[11].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[12].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[13].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[14].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[15].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[16].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[17].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[18].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[19].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[20].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[21].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[22].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[23].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[24].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[25].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[26].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[27].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[28].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[29].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[30].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[31].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[32].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[33].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[34].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[35].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[36].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[37].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[38].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[39].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[40].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[41].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[42].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[43].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[44].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[45].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[46].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[47].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[48].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[49].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[50].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[51].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[52].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[53].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[54].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[55].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[56].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[57].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[58].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[59].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[60].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[61].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[62].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[63].portbaddr[] = ( address_b_wire[1..0]); ram_block1a[63..0].portbrewe = B"1111111111111111111111111111111111111111111111111111111111111111"; address_a_wire[] = address_a[]; address_b_wire[] = address_b[]; q_b[] = ( ram_block1a[63..0].portbdataout[0..0]); END; --VALID FILE