www.pudn.com > project_2.zip > ram.vhd, change:2015-12-08,size:605b


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram is
    port(clk, en: in std_logic; cin: in std_logic_vector(511 downto 0); cout: out std_logic_vector(511 downto 0); c_en: out std_logic);
end ram;

architecture Behavioral of ram is

begin
    process(clk, en)
    variable tmp: std_logic;
    begin
        if(clk'event and clk='1')then
            if(en='1' and tmp/='1')then
                cout<=cin;
                c_en<='1';
            else
                c_en<='0';
            end if;
            tmp:=en;
        end if;
    end process;

end Behavioral;