www.pudn.com > project_2.zip > fft_unit.vhd, change:2015-12-04,size:2314b

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fft_unit is
    Port (clk, en: in std_logic; a, b, c, d, x, y: in std_logic_vector(31 downto 0); cout1, cout2, cout3, cout4: out std_logic_vector(31 downto 0); c_en: out std_logic);
end fft_unit;

architecture Behavioral of fft_unit is

component real_multiply is
    port(clk, en: in std_logic; cin1, cin2: in std_logic_vector(31 downto 0); cout: out std_logic_vector(31 downto 0); c_en: out std_logic);
end component;

component real_add is
    port(clk, en: in std_logic; cin1, cin2: in std_logic_vector(31 downto 0); cout: out std_logic_vector(31 downto 0); c_en: out std_logic);
end component;

component real_sub is
    port(clk, en: in std_logic; cin1, cin2: in std_logic_vector(31 downto 0); cout: out std_logic_vector(31 downto 0); c_en: out std_logic);
end component;

signal cx, dy, cy, dx, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8: std_logic_vector(31 downto 0);
signal cx_en, cy_en, dy_en, dx_en, tmp1_en, tmp2_en, tmp3_en, tmp4_en, f1, f2, f3, f4: std_logic;

begin
    m1: real_multiply port map(clk=>clk, en=>en, cin1=>c, cin2=>x, cout=>cx, c_en=>cx_en); 
    m2: real_multiply port map(clk=>clk, en=>en, cin1=>c, cin2=>y, cout=>cy, c_en=>cy_en);
    m3: real_multiply port map(clk=>clk, en=>en, cin1=>d, cin2=>x, cout=>dx, c_en=>dx_en);
    m4: real_multiply port map(clk=>clk, en=>en, cin1=>d, cin2=>y, cout=>dy, c_en=>dy_en);
    a11: real_add port map(clk=>clk, en=>cx_en, cin1=>a, cin2=>cx, cout=>tmp1, c_en=>tmp1_en);
    a12: real_sub port map(clk=>clk, en=>tmp1_en, cin1=>tmp1, cin2=>dy, cout=>tmp5, c_en=>f1);
    a21: real_add port map(clk=>clk, en=>cy_en, cin1=>b, cin2=>cy, cout=>tmp2, c_en=>tmp2_en);
    a22: real_add port map(clk=>clk, en=>tmp2_en, cin1=>tmp2, cin2=>dx, cout=>tmp6, c_en=>f2);
    a31: real_sub port map(clk=>clk, en=>cx_en, cin1=>a, cin2=>cx, cout=>tmp3, c_en=>tmp3_en);
    a32: real_add port map(clk=>clk, en=>tmp3_en, cin1=>tmp3, cin2=>dy, cout=>tmp7, c_en=>f3);
    a41: real_sub port map(clk=>clk, en=>cy_en, cin1=>b, cin2=>cy, cout=>tmp4, c_en=>tmp4_en);
    a42: real_sub port map(clk=>clk, en=>tmp4_en, cin1=>tmp4, cin2=>dx, cout=>tmp8, c_en=>f4);
    c_en<=f1 and f2 and f3 and f4;
    cout1<=tmp5;
    cout2<=tmp6;
    cout3<=tmp7;
    cout4<=tmp8;
end Behavioral;