www.pudn.com > project_2.zip > fft.vhd, change:2015-12-09,size:3318b


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fft is
    port(clk, reset: in std_logic; cin: in std_logic_vector(511 downto 0); cout: out std_logic_vector(511 downto 0); c_en: out std_logic);
end fft;

architecture Behavioral of fft is

component cauculator is
    port(clk, en: in std_logic; cin0: in integer; cin1: in std_logic_vector(511 downto 0); cin2: in std_logic_vector(255 downto 0); c_en: out std_logic; cout: out std_logic_vector(511 downto 0));
end component;

component counter is
    port(clk, en, reset: in std_logic;  cout: out integer; c_en: out std_logic);
end component;

component ram is
    port(clk, en: in std_logic; cin: in std_logic_vector(511 downto 0); cout: out std_logic_vector(511 downto 0); c_en: out std_logic);
end component;

component refractor is
    port(clk, en: in std_logic; cin: in std_logic_vector(511 downto 0); cout: out std_logic_vector(511 downto 0); c_en: out std_logic);
end component;

signal cout_refractor, cout_ram, cout_cauculator, cin_ram: std_logic_vector(511 downto 0);
signal cout_counter: integer range 0 to 3;
signal en_ram, c_en_refractor, c_en_ram, c_en_counter, c_en_cauculator: std_logic;
signal cin_e: std_logic_vector(255 downto 0);

begin
    u1: refractor port map(clk=>clk, en=>reset, cin=>cin, cout=>cout_refractor, c_en=>c_en_refractor);
    u2: ram port map(clk=>clk, en=>en_ram, cin=>cin_ram, cout=>cout_ram, c_en=>c_en_ram);
    u3: counter port map(clk=>clk, reset=>reset, en=>c_en_ram, cout=>cout_counter, c_en=>c_en_counter);
    u4: cauculator port map(clk=>clk, en=>c_en_counter, cin0=>cout_counter, cin1=>cout_ram, cin2=>cin_e, c_en=>c_en_cauculator, cout=>cout_cauculator);

    
    p2: process(clk, reset)
    variable tmp: std_logic;
    begin
        if(clk' event and clk='1')then
            if(reset='1' and tmp/='1')then
                cin_e(255 downto 224)<="00111111100000000000000000000000";
                cin_e(223 downto 192)<="00000000000000000000000000000000";
                cin_e(191 downto 160)<="00111111001101010000010010000000";
                cin_e(159 downto 128)<="10111111001101010000010010000000";
                cin_e(127 downto  96)<="00000000000000000000000000000000";
                cin_e(95  downto  64)<="10111111100000000000000000000000";
                cin_e(63  downto  32)<="10111111001101010000010010000000";
                cin_e(31  downto   0)<="10111111001101010000010010000000";
            else
                if(cout_counter=3)then
                    en_ram<='0';
                else
                    if(c_en_refractor='1')then
                        cin_ram<=cout_refractor;
                    else
                        cin_ram<=cout_cauculator;
                    end if;
                    en_ram<=c_en_refractor or c_en_cauculator;
                end if;
            end if;
            tmp:=reset;
        end if;
    end process p2;
    
    p3: process(clk, c_en_cauculator)
    variable tmp: std_logic;
    begin
        if(clk' event and clk='1')then
            if(c_en_cauculator='1' and tmp/='1')then
                cout<=cout_cauculator;
                c_en<='1';
            else
                c_en<='0';
            end if;
            tmp:=c_en_cauculator;
        end if;
    end process p3;
    
end Behavioral;