www.pudn.com > project_2.zip > counter.vhd, change:2016-01-05,size:926b


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
    port (clk, en, reset: in std_logic; cout: out integer; c_en: out std_logic);
end counter;

architecture Behavioral of counter is
signal count: integer range 0 to 3;
begin
    p1: process(clk, reset, en)
    variable tmp: std_logic;
    variable tmp1: std_logic;
    begin
        
        if(clk' event and clk='1')then
            if(reset='1'and tmp1/='1')then
                    count<=0;
                    c_en<='0';
            elsif(en='1' and tmp/='1' and count/=3)then
                count<=count+1;
                c_en<='1';
            elsif(en='1' and tmp/='1' and count=3)then
                count<=0;
                c_en<='1';
            else
                c_en<='0';
            end if;
            tmp:=en;
            tmp1:=reset;
        end if;
    end process p1;
    cout<=count;

end Behavioral;