www.pudn.com > project_2.zip > test_bench.vhd, change:2016-01-04,size:3311b


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity test_bench is
end test_bench;

architecture behavior of test_bench is
component cauculator is
     Port (clk, en: in std_logic; cin0: in integer; cin1: in std_logic_vector(511 downto 0); cin2: in std_logic_vector(255 downto 0); c_en: out std_logic; cout: out std_logic_vector(511 downto 0));
end component;

component real_show is
    port(clk, en: in std_logic; cin: in std_logic_vector(511 downto 0); cout1, cout2, cout3, cout4, cout5, cout6, cout7, cout8, cout9, cout10, cout11, cout12, cout13, cout14, cout15, cout16: out real);
end component;

signal clk, en, c_en: std_logic;
signal cin0: integer;
signal cin1, cout: std_logic_vector(511 downto 0);
signal cin2: std_logic_vector(255 downto 0);
signal cout1, cout2, cout3, cout4, cout5, cout6, cout7, cout8, cout9, cout10, cout11, cout12, cout13, cout14, cout15, cout16: real;




begin
    u0: cauculator port map(clk=>clk, en=>en, cin0=>cin0,cin1=>cin1, cin2=>cin2, cout=>cout, c_en=>c_en);
    u1: real_show port map(clk=>clk, en=>c_en, cin=>cout, cout1=>cout1, cout2=>cout2, cout3=>cout3, cout4=>cout4, cout5=>cout5, cout6=>cout6, cout7=>cout7, cout8=>cout8, cout9=>cout9, cout10=>cout10, cout11=>cout11, cout12=>cout12, cout13=>cout13, cout14=>cout14, cout15=>cout15, cout16=>cout16);
       
    clk_gen: process
    begin
        wait for 5ns;
        clk<='0';
        wait for 5ns;
        clk<='1';
    end process clk_gen;
    
    en_gen: process
    begin
       
        wait for 50ns;
        en<='1';
        wait for 90ns;
        en<='0';
        
        wait;
    end process en_gen;
    
    data_gen: process
    variable tmp: integer;
    begin
        wait for 20ns;
        cin2(255 downto 224)<="00111111100000000000000000000000";
        cin2(223 downto 192)<="00000000000000000000000000000000";
        cin2(191 downto 160)<="00111111001101010000010010000000";
        cin2(159 downto 128)<="10111111001101010000010010000000";
        cin2(127 downto  96)<="00000000000000000000000000000000";
        cin2(95  downto  64)<="10111111100000000000000000000000";
        cin2(63  downto  32)<="10111111001101010000010010000000";
        cin2(31  downto   0)<="10111111001101010000010010000000";
        
        cin0<=3;
        
        --for i in 0 to 15 loop
            --cin1(511-i*32 downto 480-i*32)<="00111111100000000000000000000000";
        --end loop;
        
        for i in 0 to 1 loop
            tmp:=i*8;
            cin1(511-tmp*32 downto 480-tmp*32)<="01000000100000000000000000000000";
            cin1(511-(tmp+1)*32 downto 480-(tmp+1)*32)<="01000000100000000000000000000000";
            cin1(511-(tmp+2)*32 downto 480-(tmp+2)*32)<="00000000000000000000000000000000";
            cin1(511-(tmp+3)*32 downto 480-(tmp+3)*32)<="00000000000000000000000000000000"; 
            cin1(511-(tmp+4)*32 downto 480-(tmp+4)*32)<="00000000000000000000000000000000";
            cin1(511-(tmp+5)*32 downto 480-(tmp+5)*32)<="00000000000000000000000000000000";
            cin1(511-(tmp+6)*32 downto 480-(tmp+6)*32)<="00000000000000000000000000000000";
            cin1(511-(tmp+7)*32 downto 480-(tmp+7)*32)<="00000000000000000000000000000000"; 
        end loop;    
        wait;
    end process data_gen;
    
   
end behavior;