www.pudn.com > project_2.zip > project1_bench.vhd, change:2016-01-03,size:2393b
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity project1_bench is end project1_bench; architecture behavior of project1_bench is component fft is port(clk, reset: in std_logic; cin: in std_logic_vector(511 downto 0); cout: out std_logic_vector(511 downto 0); c_en: out std_logic); end component; component real_show is port(clk, en: in std_logic; cin: in std_logic_vector(511 downto 0); cout1, cout2, cout3, cout4, cout5, cout6, cout7, cout8, cout9, cout10, cout11, cout12, cout13, cout14, cout15, cout16: out real); end component; signal clk, reset, c_en: std_logic; signal cin, cout: std_logic_vector(511 downto 0); signal cout1, cout2, cout3, cout4, cout5, cout6, cout7, cout8, cout9, cout10, cout11, cout12, cout13, cout14, cout15, cout16: real; begin u1: fft port map(clk=>clk, reset=>reset, cin=>cin, cout=>cout, c_en=>c_en); u2: real_show port map(clk=>clk, en=>c_en, cin=>cout, cout1=>cout1, cout2=>cout2, cout3=>cout3, cout4=>cout4, cout5=>cout5, cout6=>cout6, cout7=>cout7, cout8=>cout8, cout9=>cout9, cout10=>cout10, cout11=>cout11, cout12=>cout12, cout13=>cout13, cout14=>cout14, cout15=>cout15, cout16=>cout16); clk_gen: process begin wait for 2ns; clk<='0'; wait for 2ns; clk<='1'; end process clk_gen; en_gen: process begin wait for 10ns; reset<='1'; wait for 70ns; reset<='0'; wait; end process en_gen; data_gen: process begin wait for 10ns; cin(255 downto 224)<="00111111100000000000000000000000"; -- 1 cin(223 downto 192)<="11000000000110101000001001000000"; -- -2.4142 cin(191 downto 160)<="00000000000000000000000000000000"; -- 0 cin(159 downto 128)<="00000000000000000000000000000000"; -- 0 cin(127 downto 96)<="01000000000110101000001001000000"; -- 2.4142 cin(95 downto 64)<="00111111100000000000000000000000"; -- 1 cin(63 downto 32)<="00111111000101011111011011111101"; -- 0.5858 cin(31 downto 0)<="00111111101101010000010010000001"; -- 1.4142 cin(511 downto 256)<=(others=> '0'); for i in 0 to 7 loop cin(511-i*32 downto 480-i*32)<="00111111100000000000000000000000"; end loop; end process data_gen; end behavior;