www.pudn.com > project_2.zip > multiply_test.vhd, change:2016-01-04,size:1506b


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multiply_test is
end multiply_test;

architecture Behavioral of multiply_test is

component fft_unit is
    Port (clk, en: in std_logic; a, b, c, d, x, y: in std_logic_vector(31 downto 0); cout1, cout2, cout3, cout4: out std_logic_vector(31 downto 0); c_en: out std_logic);
end component;

signal clk, en, c_en: std_logic;
signal a, b, c, d, x, y, cout1, cout2, cout3, cout4: std_logic_vector(31 downto 0);

begin
    u0: fft_unit port map(clk=>clk, en=>en, c_en=>c_en, a=>a, b=>b, c=>c, d=>d, x=>x, y=>y, cout1=>cout1, cout2=>cout2, cout3=>cout3, cout4=>cout4);
    
    clk_gen: process
        begin
            wait for 5ns;
            clk<='0';
            wait for 5ns;
            clk<='1';
        end process clk_gen;
        
        en_gen: process
        begin
            wait for 50ns;
            en<='1';
            wait for 90ns;
            en<='0';
            wait;
        end process en_gen;
        
        data_gen: process
        begin
            wait for 20ns;
            a<="00111111000101011111011011111101";   -- 0.5858
            b<="00111111100000000000000000000000";   -- 1
            c<="01000000000110101000001001000000";   -- 2.4142
            d<="00111111101101010000010010000001";   -- 1.4142
            x<="00111111001101010000010010000000";   --exp(-)
            y<="10111111001101010000010010000000";
            wait;
        end process data_gen;
    
end Behavioral;