www.pudn.com > project_2.zip > fft.vds, change:2016-01-05,size:76615b
#----------------------------------------------------------- # Vivado v2015.2 (64-bit) # SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 # IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 # Start of session at: Tue Jan 05 13:17:35 2016 # Process ID: 5168 # Log file: D:/Xilinx_Project/project_2/project_2.runs/synth_1/fft.vds # Journal file: D:/Xilinx_Project/project_2/project_2.runs/synth_1\vivado.jou #----------------------------------------------------------- source fft.tcl -notrace Command: synth_design -top fft -part xc7z010clg400-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 262.906 ; gain = 86.840 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'fft' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft.vhd:9] INFO: [Synth 8-3491] module 'refractor' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/refractor.vhd:5' bound to instance 'u1' of component 'refractor' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft.vhd:33] INFO: [Synth 8-638] synthesizing module 'refractor' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/refractor.vhd:9] INFO: [Synth 8-256] done synthesizing module 'refractor' (1#1) [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/refractor.vhd:9] INFO: [Synth 8-3491] module 'ram' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/ram.vhd:5' bound to instance 'u2' of component 'ram' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft.vhd:34] INFO: [Synth 8-638] synthesizing module 'ram' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/ram.vhd:9] INFO: [Synth 8-256] done synthesizing module 'ram' (2#1) [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/ram.vhd:9] INFO: [Synth 8-3491] module 'counter' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/counter.vhd:5' bound to instance 'u3' of component 'counter' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft.vhd:35] INFO: [Synth 8-638] synthesizing module 'counter' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/counter.vhd:9] INFO: [Synth 8-256] done synthesizing module 'counter' (3#1) [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/counter.vhd:9] INFO: [Synth 8-3491] module 'cauculator' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:5' bound to instance 'u4' of component 'cauculator' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft.vhd:36] INFO: [Synth 8-638] synthesizing module 'cauculator' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:9] INFO: [Synth 8-3491] module 'fft_unit' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:5' bound to instance 'u1' of component 'fft_unit' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:20] INFO: [Synth 8-638] synthesizing module 'fft_unit' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:9] INFO: [Synth 8-3491] module 'real_multiply' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:6' bound to instance 'm1' of component 'real_multiply' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:27] INFO: [Synth 8-638] synthesizing module 'real_multiply' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:10] WARNING: [Synth 8-614] signal 'cin1' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:27] WARNING: [Synth 8-614] signal 'cin2' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:27] WARNING: [Synth 8-614] signal 'tmp2' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:27] WARNING: [Synth 8-614] signal 'tmp1' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:27] INFO: [Synth 8-256] done synthesizing module 'real_multiply' (4#1) [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:10] INFO: [Synth 8-3491] module 'real_multiply' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:6' bound to instance 'm2' of component 'real_multiply' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:28] INFO: [Synth 8-3491] module 'real_multiply' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:6' bound to instance 'm3' of component 'real_multiply' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:29] INFO: [Synth 8-3491] module 'real_multiply' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:6' bound to instance 'm4' of component 'real_multiply' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:30] INFO: [Synth 8-3491] module 'real_add' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:5' bound to instance 'a11' of component 'real_add' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:31] INFO: [Synth 8-638] synthesizing module 'real_add' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:9] WARNING: [Synth 8-614] signal 'cin1' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:30] WARNING: [Synth 8-614] signal 'cin2' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:30] INFO: [Synth 8-256] done synthesizing module 'real_add' (5#1) [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:9] INFO: [Synth 8-3491] module 'real_sub' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:5' bound to instance 'a12' of component 'real_sub' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:32] INFO: [Synth 8-638] synthesizing module 'real_sub' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:9] WARNING: [Synth 8-614] signal 'cin1' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:30] WARNING: [Synth 8-614] signal 'cin2' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:30] INFO: [Synth 8-256] done synthesizing module 'real_sub' (6#1) [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:9] INFO: [Synth 8-3491] module 'real_add' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:5' bound to instance 'a21' of component 'real_add' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:33] INFO: [Synth 8-3491] module 'real_add' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:5' bound to instance 'a22' of component 'real_add' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:34] INFO: [Synth 8-3491] module 'real_sub' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:5' bound to instance 'a31' of component 'real_sub' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:35] INFO: [Synth 8-3491] module 'real_add' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:5' bound to instance 'a32' of component 'real_add' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:36] INFO: [Synth 8-3491] module 'real_sub' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:5' bound to instance 'a41' of component 'real_sub' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:37] INFO: [Synth 8-3491] module 'real_sub' declared at 'D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:5' bound to instance 'a42' of component 'real_sub' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:38] INFO: [Synth 8-256] done synthesizing module 'fft_unit' (7#1) [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd:9] WARNING: [Synth 8-614] signal 'cin0' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:46] WARNING: [Synth 8-614] signal 'cin1' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:46] WARNING: [Synth 8-614] signal 'cin2' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:46] WARNING: [Synth 8-614] signal 'cout1' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:46] WARNING: [Synth 8-614] signal 'cout2' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:46] WARNING: [Synth 8-614] signal 'cout3' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:46] WARNING: [Synth 8-614] signal 'cout4' is read in the process but is not in the sensitivity list [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:46] INFO: [Synth 8-256] done synthesizing module 'cauculator' (8#1) [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:9] INFO: [Synth 8-256] done synthesizing module 'fft' (9#1) [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft.vhd:9] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 306.852 ; gain = 130.785 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 306.852 ; gain = 130.785 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 306.852 ; gain = 130.785 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z010clg400-1 WARNING: [Synth 8-3936] Found unconnected internal register 'v6_reg' and it is trimmed from '25' to '24' bits. [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:207] INFO: [Synth 8-5545] ROM "cout" won't be mapped to RAM because address size (32) is larger than maximum supported(18) WARNING: [Synth 8-3936] Found unconnected internal register 'v6_reg' and it is trimmed from '25' to '24' bits. [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:215] INFO: [Synth 8-5545] ROM "cout" won't be mapped to RAM because address size (32) is larger than maximum supported(18) INFO: [Synth 8-5544] ROM "start" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "tmp0" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "f_en" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "c_en" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "en_ram" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "cin_ram" won't be mapped to Block RAM because address size (2) smaller than threshold (5) WARNING: [Synth 8-327] inferring latch for variable 'c_en_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:72] WARNING: [Synth 8-327] inferring latch for variable 'cout_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:54] WARNING: [Synth 8-327] inferring latch for variable 'v4_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:42] WARNING: [Synth 8-327] inferring latch for variable 'v2_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:45] WARNING: [Synth 8-327] inferring latch for variable 'v3_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:40] WARNING: [Synth 8-327] inferring latch for variable 'tmp2_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:38] WARNING: [Synth 8-327] inferring latch for variable 'tmp1_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd:36] WARNING: [Synth 8-327] inferring latch for variable 'cout_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:210] WARNING: [Synth 8-327] inferring latch for variable 'v5_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:41] WARNING: [Synth 8-327] inferring latch for variable 'v4_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:39] WARNING: [Synth 8-327] inferring latch for variable 'v0_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:44] WARNING: [Synth 8-327] inferring latch for variable 'v6_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd:207] WARNING: [Synth 8-327] inferring latch for variable 'cout_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:218] WARNING: [Synth 8-327] inferring latch for variable 'c_en_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:322] WARNING: [Synth 8-327] inferring latch for variable 'v5_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:45] WARNING: [Synth 8-327] inferring latch for variable 'v4_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:43] WARNING: [Synth 8-327] inferring latch for variable 'v0_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:48] WARNING: [Synth 8-327] inferring latch for variable 'v6_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:215] WARNING: [Synth 8-327] inferring latch for variable 's2_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:40] WARNING: [Synth 8-327] inferring latch for variable 's1_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd:39] WARNING: [Synth 8-327] inferring latch for variable 'c_en_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:108] WARNING: [Synth 8-327] inferring latch for variable 'cout_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:101] WARNING: [Synth 8-327] inferring latch for variable 'v_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:55] WARNING: [Synth 8-327] inferring latch for variable 'step_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:53] WARNING: [Synth 8-327] inferring latch for variable 'f_en_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:20] WARNING: [Synth 8-327] inferring latch for variable 'a_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:20] WARNING: [Synth 8-327] inferring latch for variable 'b_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:20] WARNING: [Synth 8-327] inferring latch for variable 'c_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:20] WARNING: [Synth 8-327] inferring latch for variable 'd_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:20] WARNING: [Synth 8-327] inferring latch for variable 'x_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:20] WARNING: [Synth 8-327] inferring latch for variable 'y_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:20] WARNING: [Synth 8-327] inferring latch for variable 'tmp0_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd:54] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 486.934 ; gain = 310.867 --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------+------------+----------+ |1 |fft_unit__GB0 | 1| 20258| |2 |fft_unit__GB1 | 1| 15168| |3 |fft_unit__GB2 | 1| 8412| |4 |real_sub__3__GU | 1| 6756| |5 |fft_unit__GB4 | 1| 20261| |6 |cauculator__GCB0 | 1| 32640| |7 |cauculator__GCB1 | 1| 32640| |8 |cauculator__GCB2 | 1| 24480| |9 |cauculator__GCB3 | 1| 24896| |10 |cauculator__GCB4 | 1| 20592| |11 |cauculator__GCB5 | 1| 3670| |12 |cauculator__GCB6 | 1| 19716| |13 |fft__GC0 | 1| 3879| +------+-----------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 24 Input 48 Bit Adders := 4 2 Input 32 Bit Adders := 4 2 Input 31 Bit Adders := 1 2 Input 25 Bit Adders := 8 3 Input 24 Bit Adders := 16 2 Input 10 Bit Adders := 5 4 Input 9 Bit Adders := 4 2 Input 8 Bit Adders := 176 3 Input 8 Bit Adders := 24 2 Input 4 Bit Adders := 1 3 Input 3 Bit Adders := 1 2 Input 3 Bit Adders := 2 2 Input 2 Bit Adders := 13 +---Registers : 512 Bit Registers := 4 256 Bit Registers := 1 4 Bit Registers := 1 2 Bit Registers := 13 1 Bit Registers := 26 +---Muxes : 3 Input 512 Bit Muxes := 1 2 Input 512 Bit Muxes := 1 2 Input 48 Bit Muxes := 96 2 Input 32 Bit Muxes := 44 4 Input 32 Bit Muxes := 18 6 Input 32 Bit Muxes := 4 2 Input 25 Bit Muxes := 40 2 Input 24 Bit Muxes := 32 23 Input 24 Bit Muxes := 16 2 Input 23 Bit Muxes := 36 24 Input 23 Bit Muxes := 8 2 Input 22 Bit Muxes := 8 2 Input 21 Bit Muxes := 8 2 Input 20 Bit Muxes := 8 2 Input 19 Bit Muxes := 8 2 Input 18 Bit Muxes := 8 2 Input 17 Bit Muxes := 8 2 Input 16 Bit Muxes := 8 2 Input 15 Bit Muxes := 8 2 Input 14 Bit Muxes := 8 2 Input 13 Bit Muxes := 8 2 Input 12 Bit Muxes := 8 2 Input 11 Bit Muxes := 8 2 Input 10 Bit Muxes := 9 2 Input 9 Bit Muxes := 8 2 Input 8 Bit Muxes := 216 4 Input 8 Bit Muxes := 8 2 Input 7 Bit Muxes := 8 2 Input 6 Bit Muxes := 8 2 Input 5 Bit Muxes := 8 23 Input 5 Bit Muxes := 16 2 Input 4 Bit Muxes := 8 2 Input 3 Bit Muxes := 12 2 Input 2 Bit Muxes := 8 2 Input 1 Bit Muxes := 47 4 Input 1 Bit Muxes := 51 3 Input 1 Bit Muxes := 5 5 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module fft Detailed RTL Component Info : +---Registers : 512 Bit Registers := 2 256 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 512 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module real_sub__3__GU Detailed RTL Component Info : +---Adders : 2 Input 25 Bit Adders := 1 3 Input 24 Bit Adders := 2 2 Input 8 Bit Adders := 22 3 Input 8 Bit Adders := 3 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 5 2 Input 24 Bit Muxes := 4 23 Input 24 Bit Muxes := 2 2 Input 23 Bit Muxes := 4 24 Input 23 Bit Muxes := 1 2 Input 22 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 27 4 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 23 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 5 Module real_sub__1 Detailed RTL Component Info : +---Adders : 2 Input 25 Bit Adders := 1 3 Input 24 Bit Adders := 2 2 Input 8 Bit Adders := 22 3 Input 8 Bit Adders := 3 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 5 2 Input 24 Bit Muxes := 4 23 Input 24 Bit Muxes := 2 2 Input 23 Bit Muxes := 4 24 Input 23 Bit Muxes := 1 2 Input 22 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 27 4 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 23 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 5 Module real_add__1 Detailed RTL Component Info : +---Adders : 2 Input 25 Bit Adders := 1 3 Input 24 Bit Adders := 2 2 Input 8 Bit Adders := 22 3 Input 8 Bit Adders := 3 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 5 2 Input 24 Bit Muxes := 4 23 Input 24 Bit Muxes := 2 2 Input 23 Bit Muxes := 4 24 Input 23 Bit Muxes := 1 2 Input 22 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 27 4 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 23 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 2 Input 1 Bit Muxes := 5 Module real_add__2 Detailed RTL Component Info : +---Adders : 2 Input 25 Bit Adders := 1 3 Input 24 Bit Adders := 2 2 Input 8 Bit Adders := 22 3 Input 8 Bit Adders := 3 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 5 2 Input 24 Bit Muxes := 4 23 Input 24 Bit Muxes := 2 2 Input 23 Bit Muxes := 4 24 Input 23 Bit Muxes := 1 2 Input 22 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 27 4 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 23 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 2 Input 1 Bit Muxes := 5 Module real_sub__2 Detailed RTL Component Info : +---Adders : 2 Input 25 Bit Adders := 1 3 Input 24 Bit Adders := 2 2 Input 8 Bit Adders := 22 3 Input 8 Bit Adders := 3 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 5 2 Input 24 Bit Muxes := 4 23 Input 24 Bit Muxes := 2 2 Input 23 Bit Muxes := 4 24 Input 23 Bit Muxes := 1 2 Input 22 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 27 4 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 23 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 5 Module real_multiply__1 Detailed RTL Component Info : +---Adders : 24 Input 48 Bit Adders := 1 4 Input 9 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 48 Bit Muxes := 24 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 2 6 Input 32 Bit Muxes := 1 2 Input 23 Bit Muxes := 1 4 Input 1 Bit Muxes := 3 Module real_multiply__2 Detailed RTL Component Info : +---Adders : 24 Input 48 Bit Adders := 1 4 Input 9 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 48 Bit Muxes := 24 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 2 6 Input 32 Bit Muxes := 1 2 Input 23 Bit Muxes := 1 4 Input 1 Bit Muxes := 3 Module real_multiply__3 Detailed RTL Component Info : +---Adders : 24 Input 48 Bit Adders := 1 4 Input 9 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 48 Bit Muxes := 24 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 2 6 Input 32 Bit Muxes := 1 2 Input 23 Bit Muxes := 1 4 Input 1 Bit Muxes := 3 Module real_multiply Detailed RTL Component Info : +---Adders : 24 Input 48 Bit Adders := 1 4 Input 9 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 48 Bit Muxes := 24 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 2 6 Input 32 Bit Muxes := 1 2 Input 23 Bit Muxes := 1 4 Input 1 Bit Muxes := 3 Module real_add__3 Detailed RTL Component Info : +---Adders : 2 Input 25 Bit Adders := 1 3 Input 24 Bit Adders := 2 2 Input 8 Bit Adders := 22 3 Input 8 Bit Adders := 3 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 5 2 Input 24 Bit Muxes := 4 23 Input 24 Bit Muxes := 2 2 Input 23 Bit Muxes := 4 24 Input 23 Bit Muxes := 1 2 Input 22 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 27 4 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 23 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 2 Input 1 Bit Muxes := 5 Module real_add Detailed RTL Component Info : +---Adders : 2 Input 25 Bit Adders := 1 3 Input 24 Bit Adders := 2 2 Input 8 Bit Adders := 22 3 Input 8 Bit Adders := 3 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 5 2 Input 24 Bit Muxes := 4 23 Input 24 Bit Muxes := 2 2 Input 23 Bit Muxes := 4 24 Input 23 Bit Muxes := 1 2 Input 22 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 27 4 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 23 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 4 Input 1 Bit Muxes := 4 2 Input 1 Bit Muxes := 5 Module real_sub Detailed RTL Component Info : +---Adders : 2 Input 25 Bit Adders := 1 3 Input 24 Bit Adders := 2 2 Input 8 Bit Adders := 22 3 Input 8 Bit Adders := 3 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 5 2 Input 24 Bit Muxes := 4 23 Input 24 Bit Muxes := 2 2 Input 23 Bit Muxes := 4 24 Input 23 Bit Muxes := 1 2 Input 22 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 18 Bit Muxes := 1 2 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 27 4 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 23 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 5 Module cauculator Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 4 2 Input 31 Bit Adders := 1 2 Input 10 Bit Adders := 5 2 Input 4 Bit Adders := 1 3 Input 3 Bit Adders := 1 2 Input 3 Bit Adders := 2 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 512 Bit Muxes := 1 4 Input 32 Bit Muxes := 6 2 Input 32 Bit Muxes := 4 2 Input 10 Bit Muxes := 1 2 Input 3 Bit Muxes := 4 3 Input 1 Bit Muxes := 5 2 Input 1 Bit Muxes := 4 4 Input 1 Bit Muxes := 3 5 Input 1 Bit Muxes := 1 Module refractor Detailed RTL Component Info : +---Registers : 512 Bit Registers := 1 1 Bit Registers := 2 Module ram Detailed RTL Component Info : +---Registers : 512 Bit Registers := 1 1 Bit Registers := 2 Module counter Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 80 (col length:40) BRAMs: 120 (col length: RAMB18 40 RAMB36 20) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:28 . Memory (MB): peak = 500.125 ; gain = 324.059 --------------------------------------------------------------------------------- Start Cross Boundary Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-4471] merging register 'u3/tmp1_reg' into 'u1/tmp_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/counter.vhd:18] INFO: [Synth 8-4471] merging register 'tmp_reg' into 'u1/tmp_reg' [D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft.vhd:43] WARNING: [Synth 8-3917] design cauculator__GCB4 has port P[4] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port P[3] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port P[2] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port P[1] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port P[0] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port b1[9] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port b1[4] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port b1[3] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port b1[2] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port b1[1] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port b1[0] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port c1[4] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port c1[3] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port c1[2] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port c1[1] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port c1[0] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port d1[4] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port d1[3] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port d1[2] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port d1[1] driven by constant 0 WARNING: [Synth 8-3917] design cauculator__GCB4 has port d1[0] driven by constant 0 --------------------------------------------------------------------------------- Finished Cross Boundary Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:02:58 . Memory (MB): peak = 507.605 ; gain = 331.539 --------------------------------------------------------------------------------- Finished Parallel Reinference : Time (s): cpu = 00:00:41 ; elapsed = 00:02:58 . Memory (MB): peak = 507.605 ; gain = 331.539 Report RTL Partitions: +------+-----------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------+------------+----------+ |1 |fft_unit__GB0 | 1| 20355| |2 |fft_unit__GB1 | 1| 17793| |3 |fft_unit__GB2 | 1| 11004| |4 |real_sub__3__GU | 1| 6789| |5 |fft_unit__GB4 | 1| 20358| |6 |cauculator__GCB0 | 1| 32896| |7 |cauculator__GCB1 | 1| 32896| |8 |cauculator__GCB2 | 1| 24672| |9 |cauculator__GCB3 | 1| 25280| |10 |cauculator__GCB4 | 1| 3536| |11 |cauculator__GCB5 | 1| 3670| |12 |cauculator__GCB6 | 1| 20738| |13 |fft__GC0 | 1| 3877| +------+-----------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-3333] propagating constant 0 across sequential element (\step_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[6] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[9] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[15] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[17] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[19] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[20] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[23] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[24] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[25] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[26] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[27] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[28] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[30] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[32] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[33] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[34] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[35] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[36] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[37] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[38] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[39] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[40] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[41] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[42] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[43] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[44] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[45] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[46] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[47] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[48] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[49] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[50] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[51] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[52] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[53] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[54] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[55] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[56] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[57] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[58] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[59] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[60] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[61] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[62] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[63] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[64] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[65] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[66] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[67] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[68] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[69] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[70] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[71] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[72] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[73] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[74] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[75] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[76] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[77] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[78] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[79] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[80] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[81] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[82] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[83] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[84] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[85] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[86] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[87] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[88] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[89] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[90] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[91] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[92] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[93] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[94] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\cin_e_reg[95] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[96] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[97] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\cin_e_reg[98] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3332] Sequential element (\v4_reg[24] ) is unused and will be removed from module real_sub__3__GU. WARNING: [Synth 8-3332] Sequential element (\v5_reg[24] ) is unused and will be removed from module real_sub__3__GU. WARNING: [Synth 8-3332] Sequential element (\v4_reg[24] ) is unused and will be removed from module real_sub__1. WARNING: [Synth 8-3332] Sequential element (\v5_reg[24] ) is unused and will be removed from module real_sub__1. WARNING: [Synth 8-3332] Sequential element (\v5_reg[24] ) is unused and will be removed from module real_add__1. WARNING: [Synth 8-3332] Sequential element (\v4_reg[24] ) is unused and will be removed from module real_add__1. WARNING: [Synth 8-3332] Sequential element (\v5_reg[24] ) is unused and will be removed from module real_add__2. WARNING: [Synth 8-3332] Sequential element (\v4_reg[24] ) is unused and will be removed from module real_add__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[46] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[45] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[44] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[43] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[42] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[41] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[40] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[39] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[38] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[37] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[36] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[35] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[34] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[33] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[32] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[31] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[30] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[29] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[28] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[27] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[26] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[25] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[24] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[23] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[22] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[21] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[20] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[19] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[18] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[17] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[16] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[15] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[14] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[13] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[12] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[11] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[10] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[9] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[8] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[7] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[6] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[5] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[4] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[3] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[2] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[1] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[0] ) is unused and will be removed from module real_multiply__1. WARNING: [Synth 8-3332] Sequential element (\v2_reg[46] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[45] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[44] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[43] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[42] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[41] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[40] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[39] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[38] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[37] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[36] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[35] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[34] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[33] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[32] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[31] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[30] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[29] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[28] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[27] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[26] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[25] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[24] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[23] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[22] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[21] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[20] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[19] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[18] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[17] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[16] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[15] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[14] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[13] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[12] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[11] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[10] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[9] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[8] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[7] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[6] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[5] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[4] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[3] ) is unused and will be removed from module real_multiply__2. WARNING: [Synth 8-3332] Sequential element (\v2_reg[2] ) is unused and will be removed from module real_multiply__2. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:01:09 ; elapsed = 00:04:22 . Memory (MB): peak = 653.230 ; gain = 477.164 --------------------------------------------------------------------------------- Finished Parallel Area Optimization : Time (s): cpu = 00:01:09 ; elapsed = 00:04:22 . Memory (MB): peak = 653.230 ; gain = 477.164 Report RTL Partitions: +------+-----------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------+------------+----------+ |1 |fft_unit__GB0 | 1| 7854| |2 |fft_unit__GB1 | 1| 9326| |3 |fft_unit__GB2 | 1| 6708| |4 |real_sub__3__GU | 1| 2618| |5 |fft_unit__GB4 | 1| 7857| |6 |cauculator__GCB0 | 1| 2268| |7 |cauculator__GCB1 | 1| 2268| |8 |cauculator__GCB2 | 1| 1701| |9 |cauculator__GCB3 | 1| 2309| |10 |cauculator__GCB4 | 1| 582| |11 |cauculator__GCB5 | 1| 1686| |12 |cauculator__GCB6 | 1| 18090| |13 |fft__GC0 | 1| 3622| +------+-----------------+------------+----------+ Finished Parallel Synthesis Optimization : Time (s): cpu = 00:01:09 ; elapsed = 00:04:22 . Memory (MB): peak = 653.230 ; gain = 477.164 --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:09 ; elapsed = 00:04:22 . Memory (MB): peak = 653.230 ; gain = 477.164 --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------+------------+----------+ |1 |fft_unit__GB0 | 1| 7854| |2 |fft_unit__GB1 | 1| 9326| |3 |fft_unit__GB2 | 1| 6708| |4 |real_sub__3__GU | 1| 2618| |5 |fft_unit__GB4 | 1| 7857| |6 |cauculator__GCB0 | 1| 2268| |7 |cauculator__GCB1 | 1| 2268| |8 |cauculator__GCB2 | 1| 1701| |9 |cauculator__GCB3 | 1| 2309| |10 |cauculator__GCB4 | 1| 582| |11 |cauculator__GCB5 | 1| 1686| |12 |cauculator__GCB6 | 1| 18090| |13 |fft__GC0 | 1| 3622| +------+-----------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:22 ; elapsed = 00:04:36 . Memory (MB): peak = 723.484 ; gain = 547.418 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:26 ; elapsed = 00:04:39 . Memory (MB): peak = 723.484 ; gain = 547.418 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:26 ; elapsed = 00:04:39 . Memory (MB): peak = 723.484 ; gain = 547.418 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:27 ; elapsed = 00:04:41 . Memory (MB): peak = 723.484 ; gain = 547.418 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports : Time (s): cpu = 00:01:28 ; elapsed = 00:04:41 . Memory (MB): peak = 723.484 ; gain = 547.418 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:01:39 ; elapsed = 00:04:53 . Memory (MB): peak = 723.484 ; gain = 547.418 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 8| |2 |CARRY4 | 738| |3 |LUT1 | 367| |4 |LUT2 | 1654| |5 |LUT3 | 2771| |6 |LUT4 | 2065| |7 |LUT5 | 2389| |8 |LUT6 | 5668| |9 |FDRE | 2099| |10 |FDSE | 2| |11 |LD | 1836| |12 |IBUF | 514| |13 |OBUF | 513| +------+-------+------+ Report Instance Areas: +------+----------+----------------+------+ | |Instance |Module |Cells | +------+----------+----------------+------+ |1 |top | | 20624| |2 | u1 |refractor | 1031| |3 | u2 |ram | 1155| |4 | u3 |counter | 24| |5 | u4 |cauculator | 15459| |6 | u1 |fft_unit | 12814| |7 | a11 |real_add | 956| |8 | a12 |real_sub | 1800| |9 | a21 |real_add_0 | 957| |10 | a22 |real_add_1 | 1292| |11 | a31 |real_sub_2 | 966| |12 | a32 |real_add_3 | 1619| |13 | a41 |real_sub_4 | 965| |14 | a42 |real_sub_5 | 1106| |15 | m1 |real_multiply | 839| |16 | m2 |real_multiply_6 | 839| |17 | m3 |real_multiply_7 | 738| |18 | m4 |real_multiply_8 | 737| +------+----------+----------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:41 ; elapsed = 00:04:55 . Memory (MB): peak = 723.484 ; gain = 547.418 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 401 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:01:37 ; elapsed = 00:04:51 . Memory (MB): peak = 723.484 ; gain = 511.129 Synthesis Optimization Complete : Time (s): cpu = 00:01:41 ; elapsed = 00:04:55 . Memory (MB): peak = 723.484 ; gain = 547.418 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 3088 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 1836 instances were transformed. LD => LDCE: 1836 instances INFO: [Common 17-83] Releasing license: Synthesis 158 Infos, 170 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:47 ; elapsed = 00:05:04 . Memory (MB): peak = 723.484 ; gain = 515.219 write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 723.484 ; gain = 0.000 report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.555 . Memory (MB): peak = 723.484 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Tue Jan 05 13:22:51 2016...