www.pudn.com > project_2.zip > fft.tcl, change:2016-01-05,size:1499b


#  
# Synthesis run script generated by Vivado 
#  
 
debug::add_scope template.lib 1 
set_msg_config -id {HDL 9-1061} -limit 100000 
set_msg_config -id {HDL 9-1654} -limit 100000 
create_project -in_memory -part xc7z010clg400-1 
 
set_param project.compositeFile.enableAutoGeneration 0 
set_param synth.vivado.isSynthRun true 
set_property webtalk.parent_dir D:/Xilinx_Project/project_2/project_2.cache/wt [current_project] 
set_property parent.project_path D:/Xilinx_Project/project_2/project_2.xpr [current_project] 
set_property default_lib xil_defaultlib [current_project] 
set_property target_language Verilog [current_project] 
read_vhdl -library xil_defaultlib { 
  D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_sub.vhd 
  D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_multiply.vhd 
  D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/real_add.vhd 
  D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft_unit.vhd 
  D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/refractor.vhd 
  D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/ram.vhd 
  D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/counter.vhd 
  D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/cauculator.vhd 
  D:/Xilinx_Project/project_2/project_2.srcs/sources_1/new/fft.vhd 
} 
synth_design -top fft -part xc7z010clg400-1 
write_checkpoint -noxdef fft.dcp 
catch { report_utilization -file fft_utilization_synth.rpt -pb fft_utilization_synth.pb }