www.pudn.com > traffic_control2.rar > traffic_control.vho, change:2013-03-31,size:23320b


-- Copyright (C) 1991-2008 Altera Corporation 
-- Your use of Altera Corporation's design tools, logic functions  
-- and other software and tools, and its AMPP partner logic  
-- functions, and any output files from any of the foregoing  
-- (including device programming or simulation files), and any  
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License  
-- Subscription Agreement, Altera MegaCore Function License  
-- Agreement, or other applicable license agreement, including,  
-- without limitation, that your use is for the sole purpose of  
-- programming logic devices manufactured by Altera and sold by  
-- Altera or its authorized distributors.  Please refer to the  
-- applicable agreement for further details. 
 
-- VENDOR "Altera" 
-- PROGRAM "Quartus II" 
-- VERSION "Version 8.1 Build 163 10/28/2008 SJ Full Version" 
 
-- DATE "03/31/2013 10:58:46" 
 
--  
-- Device: Altera EP2S15F484C3 Package FBGA484 
--  
 
--  
-- This VHDL file should be used for ModelSim-Altera (VHDL) only 
--  
 
LIBRARY IEEE, stratixii; 
USE IEEE.std_logic_1164.all; 
USE stratixii.stratixii_components.all; 
 
ENTITY 	traffic_control IS 
    PORT ( 
	clk : IN std_logic; 
	c1 : OUT std_logic; 
	c2 : OUT std_logic; 
	c3 : OUT std_logic; 
	w1 : IN std_logic; 
	w2 : IN std_logic; 
	w3 : IN std_logic; 
	r1 : OUT std_logic; 
	r2 : OUT std_logic; 
	y1 : OUT std_logic; 
	y2 : OUT std_logic; 
	g1 : OUT std_logic; 
	g2 : OUT std_logic; 
	reset : IN std_logic 
	); 
END traffic_control; 
 
ARCHITECTURE structure OF traffic_control IS 
SIGNAL gnd : std_logic := '0'; 
SIGNAL vcc : std_logic := '1'; 
SIGNAL devoe : std_logic := '1'; 
SIGNAL devclrn : std_logic := '1'; 
SIGNAL devpor : std_logic := '1'; 
SIGNAL ww_devoe : std_logic; 
SIGNAL ww_devclrn : std_logic; 
SIGNAL ww_devpor : std_logic; 
SIGNAL ww_clk : std_logic; 
SIGNAL ww_c1 : std_logic; 
SIGNAL ww_c2 : std_logic; 
SIGNAL ww_c3 : std_logic; 
SIGNAL ww_w1 : std_logic; 
SIGNAL ww_w2 : std_logic; 
SIGNAL ww_w3 : std_logic; 
SIGNAL ww_r1 : std_logic; 
SIGNAL ww_r2 : std_logic; 
SIGNAL ww_y1 : std_logic; 
SIGNAL ww_y2 : std_logic; 
SIGNAL ww_g1 : std_logic; 
SIGNAL ww_g2 : std_logic; 
SIGNAL ww_reset : std_logic; 
SIGNAL \clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); 
SIGNAL \reset~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); 
SIGNAL \clk~combout\ : std_logic; 
SIGNAL \clk~clkctrl_outclk\ : std_logic; 
SIGNAL \w2~combout\ : std_logic; 
SIGNAL \w3~combout\ : std_logic; 
SIGNAL \w1~combout\ : std_logic; 
SIGNAL \Selector2~53_combout\ : std_logic; 
SIGNAL \reset~combout\ : std_logic; 
SIGNAL \reset~clkctrl_outclk\ : std_logic; 
SIGNAL \state.S2~regout\ : std_logic; 
SIGNAL \Selector1~223_combout\ : std_logic; 
SIGNAL \state.S1~regout\ : std_logic; 
SIGNAL \state.S0~272_combout\ : std_logic; 
SIGNAL \state.S0~regout\ : std_logic; 
SIGNAL \Selector1~222_combout\ : std_logic; 
SIGNAL \state.S3~191_combout\ : std_logic; 
SIGNAL \state.S3~regout\ : std_logic; 
SIGNAL \c2~0_combout\ : std_logic; 
SIGNAL \r1~0_combout\ : std_logic; 
SIGNAL \r2~0_combout\ : std_logic; 
SIGNAL \ALT_INV_state.S0~regout\ : std_logic; 
SIGNAL \ALT_INV_state.S1~regout\ : std_logic; 
SIGNAL \ALT_INV_state.S3~regout\ : std_logic; 
SIGNAL \ALT_INV_state.S2~regout\ : std_logic; 
SIGNAL \ALT_INV_Selector1~222_combout\ : std_logic; 
SIGNAL \ALT_INV_w2~combout\ : std_logic; 
SIGNAL \ALT_INV_w1~combout\ : std_logic; 
SIGNAL \ALT_INV_w3~combout\ : std_logic; 
 
BEGIN 
 
ww_clk <= clk; 
c1 <= ww_c1; 
c2 <= ww_c2; 
c3 <= ww_c3; 
ww_w1 <= w1; 
ww_w2 <= w2; 
ww_w3 <= w3; 
r1 <= ww_r1; 
r2 <= ww_r2; 
y1 <= ww_y1; 
y2 <= ww_y2; 
g1 <= ww_g1; 
g2 <= ww_g2; 
ww_reset <= reset; 
ww_devoe <= devoe; 
ww_devclrn <= devclrn; 
ww_devpor <= devpor; 
 
\clk~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\); 
 
\reset~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \reset~combout\); 
\ALT_INV_state.S0~regout\ <= NOT \state.S0~regout\; 
\ALT_INV_state.S1~regout\ <= NOT \state.S1~regout\; 
\ALT_INV_state.S3~regout\ <= NOT \state.S3~regout\; 
\ALT_INV_state.S2~regout\ <= NOT \state.S2~regout\; 
\ALT_INV_Selector1~222_combout\ <= NOT \Selector1~222_combout\; 
\ALT_INV_w2~combout\ <= NOT \w2~combout\; 
\ALT_INV_w1~combout\ <= NOT \w1~combout\; 
\ALT_INV_w3~combout\ <= NOT \w3~combout\; 
 
\clk~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "input", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => GND, 
	padio => ww_clk, 
	combout => \clk~combout\); 
 
\clk~clkctrl\ : stratixii_clkctrl 
-- pragma translate_off 
GENERIC MAP ( 
	clock_type => "global clock") 
-- pragma translate_on 
PORT MAP ( 
	inclk => \clk~clkctrl_INCLK_bus\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	outclk => \clk~clkctrl_outclk\); 
 
\w2~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "input", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => GND, 
	padio => ww_w2, 
	combout => \w2~combout\); 
 
\w3~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "input", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => GND, 
	padio => ww_w3, 
	combout => \w3~combout\); 
 
\w1~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "input", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => GND, 
	padio => ww_w1, 
	combout => \w1~combout\); 
 
\Selector2~53\ : stratixii_lcell_comb 
-- Equation(s): 
-- \Selector2~53_combout\ = \state.S1~regout\ & ( !\w2~combout\ & (!\w3~combout\ & \state.S2~regout\) # \w2~combout\ & !\state.S3~regout\ ) # !\state.S1~regout\ & ( !\w3~combout\ & \state.S2~regout\ & (!\state.S3~regout\ # !\w2~combout\) ) 
 
-- pragma translate_off 
GENERIC MAP ( 
	extended_lut => "off", 
	lut_mask => "0000000011100000000000001110000000100010111000100010001011100010", 
	shared_arith => "off") 
-- pragma translate_on 
PORT MAP ( 
	dataa => \ALT_INV_state.S3~regout\, 
	datab => \ALT_INV_w2~combout\, 
	datac => \ALT_INV_w3~combout\, 
	datad => \ALT_INV_state.S2~regout\, 
	dataf => \ALT_INV_state.S1~regout\, 
	combout => \Selector2~53_combout\); 
 
\reset~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "input", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => GND, 
	padio => ww_reset, 
	combout => \reset~combout\); 
 
\reset~clkctrl\ : stratixii_clkctrl 
-- pragma translate_off 
GENERIC MAP ( 
	clock_type => "global clock") 
-- pragma translate_on 
PORT MAP ( 
	inclk => \reset~clkctrl_INCLK_bus\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	outclk => \reset~clkctrl_outclk\); 
 
\state.S2\ : stratixii_lcell_ff 
PORT MAP ( 
	clk => \clk~clkctrl_outclk\, 
	datain => \Selector2~53_combout\, 
	aclr => \reset~clkctrl_outclk\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	regout => \state.S2~regout\); 
 
\Selector1~223\ : stratixii_lcell_comb 
-- Equation(s): 
-- \Selector1~223_combout\ = \state.S1~regout\ & \state.S2~regout\ & ( !\w3~combout\ & (!\w2~combout\ # !\state.S0~regout\ & \w1~combout\) ) # !\state.S1~regout\ & \state.S2~regout\ & ( !\w3~combout\ & !\state.S0~regout\ & \w1~combout\ ) # \state.S1~regout\  
-- & !\state.S2~regout\ & ( !\w2~combout\ # !\state.S0~regout\ & \w1~combout\ ) # !\state.S1~regout\ & !\state.S2~regout\ & ( !\state.S0~regout\ & \w1~combout\ ) 
 
-- pragma translate_off 
GENERIC MAP ( 
	extended_lut => "off", 
	lut_mask => "0000000011110000101010101111101000000000110000001000100011001000", 
	shared_arith => "off") 
-- pragma translate_on 
PORT MAP ( 
	dataa => \ALT_INV_w2~combout\, 
	datab => \ALT_INV_w3~combout\, 
	datac => \ALT_INV_state.S0~regout\, 
	datad => \ALT_INV_w1~combout\, 
	datae => \ALT_INV_state.S1~regout\, 
	dataf => \ALT_INV_state.S2~regout\, 
	combout => \Selector1~223_combout\); 
 
\state.S1\ : stratixii_lcell_ff 
PORT MAP ( 
	clk => \clk~clkctrl_outclk\, 
	datain => \Selector1~223_combout\, 
	aclr => \reset~clkctrl_outclk\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	regout => \state.S1~regout\); 
 
\state.S0~272\ : stratixii_lcell_comb 
-- Equation(s): 
-- \state.S0~272_combout\ = !\state.S2~regout\ & ( !\w2~combout\ & (\state.S0~regout\ # \w1~combout\) # \w2~combout\ & (!\state.S3~regout\ & (!\w1~combout\ $ !\state.S1~regout\ # \state.S0~regout\) # \state.S3~regout\ & (\state.S1~regout\ &  
-- \state.S0~regout\)) ) # \state.S2~regout\ & ( !\w2~combout\ & (\state.S0~regout\ # \w3~combout\) # \w2~combout\ & (!\state.S3~regout\ & (!\w3~combout\ $ !\state.S1~regout\ # \state.S0~regout\) # \state.S3~regout\ & \state.S0~regout\ & (!\w3~combout\ $  
-- !\state.S1~regout\)) ) 
 
-- pragma translate_off 
GENERIC MAP ( 
	extended_lut => "on", 
	lut_mask => "0000111000101100000011100010110011101110111111111110111111111110", 
	shared_arith => "off") 
-- pragma translate_on 
PORT MAP ( 
	dataa => \ALT_INV_state.S3~regout\, 
	datab => \ALT_INV_w2~combout\, 
	datac => \ALT_INV_w3~combout\, 
	datad => \ALT_INV_state.S1~regout\, 
	datae => \ALT_INV_state.S2~regout\, 
	dataf => \ALT_INV_state.S0~regout\, 
	datag => \ALT_INV_w1~combout\, 
	combout => \state.S0~272_combout\); 
 
\state.S0\ : stratixii_lcell_ff 
PORT MAP ( 
	clk => \clk~clkctrl_outclk\, 
	datain => \state.S0~272_combout\, 
	aclr => \reset~clkctrl_outclk\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	regout => \state.S0~regout\); 
 
\Selector1~222\ : stratixii_lcell_comb 
-- Equation(s): 
-- \Selector1~222_combout\ = \state.S2~regout\ & ( \w3~combout\ ) 
 
-- pragma translate_off 
GENERIC MAP ( 
	extended_lut => "off", 
	lut_mask => "0000000000000000000000000000000001010101010101010101010101010101", 
	shared_arith => "off") 
-- pragma translate_on 
PORT MAP ( 
	dataa => \ALT_INV_w3~combout\, 
	dataf => \ALT_INV_state.S2~regout\, 
	combout => \Selector1~222_combout\); 
 
\state.S3~191\ : stratixii_lcell_comb 
-- Equation(s): 
-- \state.S3~191_combout\ = \state.S3~regout\ & \Selector1~222_combout\ # !\state.S3~regout\ & \Selector1~222_combout\ & ( !\w1~combout\ & (!\w2~combout\ # !\state.S1~regout\) # \w1~combout\ & (!\state.S0~regout\ $ (!\w2~combout\ # !\state.S1~regout\)) ) #  
-- \state.S3~regout\ & !\Selector1~222_combout\ & ( !\w2~combout\ $ (\w1~combout\ & !\state.S0~regout\) ) 
 
-- pragma translate_off 
GENERIC MAP ( 
	extended_lut => "off", 
	lut_mask => "0000000000000000100110011100110010101001111111001111111111111111", 
	shared_arith => "off") 
-- pragma translate_on 
PORT MAP ( 
	dataa => \ALT_INV_w1~combout\, 
	datab => \ALT_INV_w2~combout\, 
	datac => \ALT_INV_state.S1~regout\, 
	datad => \ALT_INV_state.S0~regout\, 
	datae => \ALT_INV_state.S3~regout\, 
	dataf => \ALT_INV_Selector1~222_combout\, 
	combout => \state.S3~191_combout\); 
 
\state.S3\ : stratixii_lcell_ff 
PORT MAP ( 
	clk => \clk~clkctrl_outclk\, 
	datain => \state.S3~191_combout\, 
	aclr => \reset~clkctrl_outclk\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	regout => \state.S3~regout\); 
 
\c2~0\ : stratixii_lcell_comb 
-- Equation(s): 
-- \c2~0_combout\ = \state.S3~regout\ # !\state.S3~regout\ & ( \state.S1~regout\ ) 
 
-- pragma translate_off 
GENERIC MAP ( 
	extended_lut => "off", 
	lut_mask => "0011001100110011001100110011001111111111111111111111111111111111", 
	shared_arith => "off") 
-- pragma translate_on 
PORT MAP ( 
	datab => \ALT_INV_state.S1~regout\, 
	dataf => \ALT_INV_state.S3~regout\, 
	combout => \c2~0_combout\); 
 
\r1~0\ : stratixii_lcell_comb 
-- Equation(s): 
-- \r1~0_combout\ = \state.S0~regout\ & ( \state.S1~regout\ ) # !\state.S0~regout\ 
 
-- pragma translate_off 
GENERIC MAP ( 
	extended_lut => "off", 
	lut_mask => "1111111111111111111111111111111100110011001100110011001100110011", 
	shared_arith => "off") 
-- pragma translate_on 
PORT MAP ( 
	datab => \ALT_INV_state.S1~regout\, 
	dataf => \ALT_INV_state.S0~regout\, 
	combout => \r1~0_combout\); 
 
\r2~0\ : stratixii_lcell_comb 
-- Equation(s): 
-- \r2~0_combout\ = \state.S2~regout\ # !\state.S2~regout\ & ( \state.S3~regout\ ) 
 
-- pragma translate_off 
GENERIC MAP ( 
	extended_lut => "off", 
	lut_mask => "0101010101010101010101010101010111111111111111111111111111111111", 
	shared_arith => "off") 
-- pragma translate_on 
PORT MAP ( 
	dataa => \ALT_INV_state.S3~regout\, 
	dataf => \ALT_INV_state.S2~regout\, 
	combout => \r2~0_combout\); 
 
\c1~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "output", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	datain => \ALT_INV_state.S0~regout\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => VCC, 
	padio => ww_c1); 
 
\c2~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "output", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	datain => \c2~0_combout\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => VCC, 
	padio => ww_c2); 
 
\c3~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "output", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	datain => \state.S2~regout\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => VCC, 
	padio => ww_c3); 
 
\r1~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "output", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	datain => \r1~0_combout\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => VCC, 
	padio => ww_r1); 
 
\r2~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "output", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	datain => \r2~0_combout\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => VCC, 
	padio => ww_r2); 
 
\y1~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "output", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	datain => \state.S3~regout\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => VCC, 
	padio => ww_y1); 
 
\y2~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "output", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	datain => \state.S1~regout\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => VCC, 
	padio => ww_y2); 
 
\g1~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "output", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	datain => \state.S2~regout\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => VCC, 
	padio => ww_g1); 
 
\g2~I\ : stratixii_io 
-- pragma translate_off 
GENERIC MAP ( 
	ddio_mode => "none", 
	ddioinclk_input => "negated_inclk", 
	dqs_delay_buffer_mode => "none", 
	dqs_out_mode => "none", 
	inclk_input => "normal", 
	input_async_reset => "none", 
	input_power_up => "low", 
	input_register_mode => "none", 
	input_sync_reset => "none", 
	oe_async_reset => "none", 
	oe_power_up => "low", 
	oe_register_mode => "none", 
	oe_sync_reset => "none", 
	operation_mode => "output", 
	output_async_reset => "none", 
	output_power_up => "low", 
	output_register_mode => "none", 
	output_sync_reset => "none", 
	sim_dqs_delay_increment => 0, 
	sim_dqs_intrinsic_delay => 0, 
	sim_dqs_offset_increment => 0) 
-- pragma translate_on 
PORT MAP ( 
	datain => \ALT_INV_state.S0~regout\, 
	devclrn => ww_devclrn, 
	devpor => ww_devpor, 
	devoe => ww_devoe, 
	oe => VCC, 
	padio => ww_g2); 
END structure;