www.pudn.com > S3c2410bsp.zip > romInit.s
/* romInit.s - Samsung SBC ARM9 ROM initialization module */
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "arch/arm/arm.h"
#include "arch/arm/mmuArmLib.h"
#include "config.h"
#include "regs.h"
.data
.globl FUNC(copyright_wind_river)
.long FUNC(copyright_wind_river)
/* internals */
.globl FUNC(romInit) /* start of system code */
.globl FUNC(sdata) /* start of data */
.globl _sdata
.globl VAR(s3c2410xMemSize) /* actual memory size */
.globl FUNC(romStart)
_sdata:
FUNC_LABEL(sdata)
.asciz "start of data"
.balign 4
.data
VAR_LABEL(s3c2410xMemSize)
.long 0
.text
.balign 4
/*******************************************************************************
*
*
*
*/
_ARM_FUNCTION(romInit)
_romInit:
B cold
B _romUndef
B _romSwi
B _romPrefetch
B _romDataAbort
B cold /* _romReserved */
B _romIRQ
B cold /* _romFIQ */
cold:
MOV r0, #BOOT_COLD
warm:
B start
.ascii "Copyright 2004-2005 "
.ascii "Copyright 1984-2001 Wind River Systems, Inc."
.balign 4
start:
LDR r2, L$_S3C2410XWtcon
LDR r1, L$_S3C2410XWtconVal
STR r1, [r2]
LDR r2, L$_SBCARM9Intmsk
MOV r1, #0xffffffff
STR r1, [r2]
LDR r2, L$_SBCARM9IntSubMsk
MOV r1, #0xffffff
STR r1, [r2]
LDR r2, L$_SBCARM9Locktime
LDR r1, L$_LockTime
STR r1, [r2]
LDR r2, L$_SBCARM9MPllcon
LDR r1, L$_MPllCon
STR r1, [r2]
LDR r2, L$_SBCARM9UPllcon
LDR r1, L$_UPllCon
STR r1, [r2]
LDR r2, L$_SBCARM9ClkCon
LDR r1, L$_ClkCon
STR r1, [r2]
LDR r2, L$_SBCARM9ClkSlow
LDR r1, L$_ClkSlow
STR r1, [r2]
LDR r2, L$_SBCARM9ClkDivn
LDR r1, L$_ClkDivn
STR r1, [r2]
MOV r13, r0
CMP r0, #BOOT_COLD
BNE HiPosn
SYNC_DRAM:
LDR r1, L$_SystemInitDataSDRAM
LDR r2, L$_SystemInitDataSDRAM + 0x04
LDR r3, L$_SystemInitDataSDRAM + 0x08
LDR r4, L$_SystemInitDataSDRAM + 0x0c
LDR r5, L$_SystemInitDataSDRAM + 0x10
LDR r6, L$_SystemInitDataSDRAM + 0x14
LDR r7, L$_SystemInitDataSDRAM + 0x18
LDR r8, L$_SystemInitDataSDRAM + 0x1c
LDR r9, L$_SystemInitDataSDRAM + 0x20
LDR r10,L$_SystemInitDataSDRAM + 0x24
LDR r11,L$_SystemInitDataSDRAM + 0x28
LDR r12,L$_SystemInitDataSDRAM + 0x2c
LDR r0, L$_SBCARM9Extdbwth
STMIA r0, {r1-r12}
LDR r0, L$_SBCARM9Mrsrb7
LDR r1, L$_SystemInitDataSDRAM +0x30
STR r1, [r0]
MOV r0, #RESET_ROM_START /* Get pointer to ROM data */
LDR r1, L$_RomCopySize /* number of ROM bytes to copy into RAM */
MOV r2, #RESET_DRAM_START /* Copy DRAM area base */
ROM2SDRAM_COPY_LOOP:
LDR r3, [r0], #4
STR r3, [r2], #4
SUBS r1, r1, #4
BNE ROM2SDRAM_COPY_LOOP
#if 0
/*====================================
* Change Base address of ROM and DRAM
*====================================
*/
/* Multiple load LDMIA instruction cannot be used as there is
* no way to load the address L$_SystemInitDataSDRAM_S into a
* register (LDR Rn,=sym is broken)
*/
LDR r1, L$_SystemInitDataSDRAM_S
LDR r2, L$_SystemInitDataSDRAM_S + 0x04
LDR r3, L$_SystemInitDataSDRAM_S + 0x08
LDR r4, L$_SystemInitDataSDRAM_S + 0x0c
LDR r5, L$_SystemInitDataSDRAM_S + 0x10
LDR r6, L$_SystemInitDataSDRAM_S + 0x14
LDR r7, L$_SystemInitDataSDRAM_S + 0x18
LDR r8, L$_SystemInitDataSDRAM_S + 0x1c
LDR r9, L$_SystemInitDataSDRAM_S + 0x20
LDR r10,L$_SystemInitDataSDRAM_S + 0x24
LDR r11,L$_SystemInitDataSDRAM_S + 0x28
LDR r12,L$_SystemInitDataSDRAM_S + 0x2c
LDR r0, L$_SBCARM9Extdbwth /* ROMCntr Offset : 0x3010 */
STMIA r0, {r1-r12}
#endif
LDR PC, L$_HiPosn
#if 0 /* : deleted */
EDO_RAM:
LDR r0, L$_SBCARM9Syscfg
LDR r1, L$_SysCfg
STR r1, [r0]
/* ROM and RAM Configuration(Multiple Load and Store)
* Multiple load LDMIA instruction cannot be used as there is
* no way to load the address L$_SystemInitData into a
* register (LDR Rn,=sym is broken)
*/
LDR r1, L$_SystemInitData
LDR r2, L$_SystemInitData + 0x04
LDR r3, L$_SystemInitData + 0x08
LDR r4, L$_SystemInitData + 0x0c
LDR r5, L$_SystemInitData + 0x10
LDR r6, L$_SystemInitData + 0x14
LDR r7, L$_SystemInitData + 0x18
LDR r8, L$_SystemInitData + 0x1c
LDR r9, L$_SystemInitData + 0x20
LDR r10,L$_SystemInitData + 0x24
LDR r11,L$_SystemInitData + 0x28
LDR r12,L$_SystemInitData + 0x2c
LDR r0, L$_SBCARM9Extdbwth /* ROMCntr Offset : 0x3010 */
STMIA r0, {r1-r12}
/*=============================================================
* Copy to DRAM the section of ROM in which we are currently executing.
* Soon, we will set the base pointer of DRAM to where the base pointer of
* ROM used to be. At that point the PC will suddenly be set in RAM and
* must have legitimate code to execute.
*=============================================================
*/
MOV r0, #RESET_ROM_START /* Get pointer to ROM data */
LDR r1, L$_RomCopySize /* number of ROM bytes to copy into RAM */
MOV r2, #RESET_DRAM_START /* Copy DRAM area base */
ROM2DRAM_COPY_LOOP:
LDR r3, [r0], #4
STR r3, [r2], #4
SUBS r1, r1, #4 /* Down Count */
BNE ROM2DRAM_COPY_LOOP
/*====================================
* Change Base address of ROM and DRAM
*====================================
*/
/* Multiple load LDMIA instruction cannot be used as there is
* no way to load the address L$_SystemInitData_S into a
* register (LDR Rn,=sym is broken)
*/
LDR r1, L$_SystemInitData_S
LDR r2, L$_SystemInitData_S + 0x04
LDR r3, L$_SystemInitData_S + 0x08
LDR r4, L$_SystemInitData_S + 0x0c
LDR r5, L$_SystemInitData_S + 0x10
LDR r6, L$_SystemInitData_S + 0x14
LDR r7, L$_SystemInitData_S + 0x18
LDR r8, L$_SystemInitData_S + 0x1c
LDR r9, L$_SystemInitData_S + 0x20
LDR r10,L$_SystemInitData_S + 0x24
LDR r11,L$_SystemInitData_S + 0x28
LDR r12,L$_SystemInitData_S + 0x2c
LDR r0, L$_SBCARM9Extdbwth
STMIA r0, {r1-r12}
LDR PC, L$_HiPosn
#endif
HiPosn:
LDR r1, =SZ_16M
LDR r3, L$_memSize
STR r1, [r3]
MOV r3, r1
MOV r0, r13
LDR sp, L$_STACK_ADDR
MOV fp, #0
#if (CPU == ARMARCH4_T)
LDR r12, L$_rStrtInRom
ORR r12, r12, #1
BX r12
#else
LDR pc, L$_rStrtInRom
#endif /* (CPU == ARMARCH4_T) */
_ARM_FUNCTION(romUndef)
_romUndef:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promUndef
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romSwi)
_romSwi:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promSwi
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romPrefetch)
_romPrefetch:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promPrefetch
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romDataAbort)
_romDataAbort:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promDataAbort
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romReserved)
_romReserved:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promReserved
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romIRQ)
_romIRQ:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promIRQ
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romFIQ)
_romFIQ:
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, L$_promFIQ
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
/******************************************************************************/
/*
* PC-relative-addressable pointers - LDR Rn,=sym is broken
* note "_" after "$" to stop preprocessor preforming substitution
*/
.balign 4
#ifdef RAM_SIM
L$_HiPosn:
.long RAM_HIGH_ADRS + HiPosn - FUNC(romInit)
L$_rStrtInRom:
.long RAM_HIGH_ADRS + FUNC(romStart) - FUNC(romInit)
#else
L$_HiPosn:
.long ROM_TEXT_ADRS + HiPosn - FUNC(romInit)
L$_rStrtInRom:
.long ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)
L$_memSize:
.long VAR(s3c2410xMemSize)
#endif
L$_STACK_ADDR:
.long STACK_ADRS
L$_SBCARM9Intmsk:
.long S3C2410X_INTMASK
L$_SBCARM9IntSubMsk:
.long S3C2410X_INTSUBMSK
L$_SBCARM9MPllcon:
.long S3C2410X_MPLLCON
L$_SBCARM9UPllcon:
.long S3C2410X_UPLLCON
L$_SBCARM9Locktime:
.long S3C2410X_LOCKTIME
L$_S3C2410XWtcon:
.long S3C2410X_WTCON
L$_S3C2410XWtconVal:
.long rWTCON_INIT_VALUE
L$_SBCARM9Romcon0:
.long S3C2410X_BANKCON0
L$_SBCARM9Extdbwth:
.long S3C2410X_BWSCON
L$_SBCARM9Mrsrb7:
.long S3C2410X_MRSRB7
L$_SysCfgSdram:
.long SYSCONFIG_VAL_SDRAM
L$_SBCARM9ClkCon:
.long S3C2410X_CLKCON
L$_SBCARM9ClkSlow:
.long S3C2410X_CLKSLOW
L$_SBCARM9ClkDivn:
.long S3C2410X_CLKDIVN
L$_ClkCon:
.long rCLKCON
L$_ClkSlow:
.long rCLKSLOW
L$_ClkDivn:
.long rCLKDIVN
L$_MPllCon:
.long rMPLLCON
L$_UPllCon:
.long rUPLLCON
L$_LockTime:
.long rLOCKTIME
L$_PortConfB:
.long S3C2410X_PCONB
L$_PortDataB:
.long S3C2410X_PDATB
/*======================================================
* SDRAM System Initialize Data (KS32C50100 only)
*======================================================
*/
L$_SystemInitDataSDRAM:
.long rEXTDBWTH
.long rROMCON0
.long rROMCON1
.long rROMCON2
.long rROMCON3
.long rROMCON4
.long rROMCON5
.long rSDRAMCON0 /* 0x1000000 ~ 0x13FFFFF, DRAM0 4M, */
.long rSDRAMCON1
.long rSREFEXTCON
.long rBANKSIZE
.long rMRSRB6
.long rMRSRB7
#if 0
L$_SystemInitDataSDRAM_S:
.long rEXTDBWTH /* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */
.long rROMCON0_S /* 0x1000000 ~ 0x1040000, ROM0,256K,2cycle */
.long rROMCON1
.long rROMCON2
.long rROMCON3
.long rROMCON4
.long rROMCON5
.long rSDRAMCON0_S /* 0x0000000 ~ 0x03FFFFF, DRAM0 4M, */
.long rSDRAMCON1
.long rSDRAMCON2
.long rSDRAMCON3
.long rSREFEXTCON /* External I/O, Refresh */
L$_pSystemInitData:
.long L$_SystemInitData
L$_pSystemInitData_S:
.long L$_SystemInitData_S
#endif
L$_pSystemInitDataSDRAM:
.long L$_SystemInitDataSDRAM
#if 0
L$_pSystemInitDataSDRAM_S:
.long L$_SystemInitDataSDRAM_S
#endif
L$_promUndef:
.long S3C_EXC_BASE
L$_promSwi:
.long S3C_EXC_BASE + 4
L$_promPrefetch:
.long S3C_EXC_BASE + 8
L$_promDataAbort:
.long S3C_EXC_BASE + 12
L$_promReserved:
.long S3C_EXC_BASE + 16
L$_promIRQ:
.long S3C_EXC_BASE + 20
L$_promFIQ:
.long S3C_EXC_BASE + 24
L$_RomCopySize:
.long L$_RomCopySize - FUNC(romInit)