www.pudn.com > 8051_pppsrc.zip > IOGP20.h, change:2000-11-19,size:5683b
/* IO DEFINITIONS FOR MC68HC08GP20
* Copyright (c) 1998 by COSMIC Software
*/
#ifndef __IOGP20_H
#define __IOGP20_H
#if HIWARE
#include <hidef.h>
#endif
#define uint unsigned int
/* PORTS section
*/
volatile char PORTA @0x00; /* port A */
volatile char PORTB @0x01; /* port B */
volatile char PORTC @0x02; /* port C */
volatile char PORTD @0x03; /* port D */
volatile char DDRA @0x04; /* data direction port A */
volatile char DDRB @0x05; /* data direction port B */
volatile char DDRC @0x06; /* data direction port C */
volatile char DDRD @0x07; /* data direction port D */
volatile char PORTE @0x08; /* port E */
volatile char DDRE @0x0c; /* data direction port E */
volatile char PTAPUE @0x0d; /* pull-up enable port A */
volatile char PTCPUE @0x0e; /* pull-up enable port C */
volatile char PTDPUE @0x0f; /* pull-up enable port D */
/* SPI section
*/
volatile char SPCR @0x10; /* SPI control register */
volatile char SPSCR @0x11; /* SPI control/status register */
volatile char SPDR @0x12; /* SPI data register */
/* SCI section
*/
volatile char SCC1 @0x13; /* SCI control register 1 */
volatile char SCC2 @0x14; /* SCI control register 2 */
volatile char SCC3 @0x15; /* SCI control register 3 */
volatile char SCS1 @0x16; /* SCI status register 1 */
volatile char SCS2 @0x17; /* SCI status register 2 */
volatile char SCDR @0x18; /* SCI data register */
volatile char SCBR @0x19; /* SCI baud rate */
/* KEYBOARD section
*/
volatile char INTKBSCR @0x1a; /* keyboard control/status */
volatile char INTKBIER @0x1b; /* keyboard interrupt enable */
/* CONFIG section
*/
volatile char TBCR @0x1c; /* time base module control */
volatile char INTSCR @0x1d; /* IRQ status/control register */
volatile char CONFIG2 @0x1e; /* configuration register 2 */
volatile char CONFIG1 @0x1f; /* configuration register 1 */
/* TIMER section
*/
volatile char T1SC @0x20; /* timer 1 status/ctrl register */
volatile uint T1CNT @0x21; /* timer 1 counter register */
volatile char T1CNTH @0x21; /* timer 1 counter high */
volatile char T1CNTL @0x22; /* timer 1 counter low */
volatile uint T1MOD @0x23; /* timer 1 modulo register */
volatile char T1MODH @0x23; /* timer 1 modulo high */
volatile char T1MODL @0x24; /* timer 1 modulo low */
volatile char T1SC0 @0x25; /* timer 1 chan 0 status/ctrl */
volatile uint T1CH0 @0x26; /* timer 1 chan 0 register */
volatile char T1CH0H @0x26; /* timer 1 chan 0 high */
volatile char T1CH0L @0x27; /* timer 1 chan 0 low */
volatile char T1SC1 @0x28; /* timer 1 chan 1 status/ctrl */
volatile uint T1CH1 @0x29; /* timer 1 chan 1 register */
volatile char T1CH1H @0x29; /* timer 1 chan 1 high */
volatile char T1CH1L @0x2a; /* timer 1 chan 1 low */
volatile char T2SC @0x2b; /* timer 2 status/ctrl register */
volatile uint T2CNT @0x2c; /* timer 2 counter register */
volatile char T2CNTH @0x2c; /* timer 2 counter high */
volatile char T2CNTL @0x2d; /* timer 2 counter low */
volatile uint T2MOD @0x2e; /* timer 2 modulo register */
volatile char T2MODH @0x2e; /* timer 2 modulo high */
volatile char T2MODL @0x2f; /* timer 2 modulo low */
volatile char T2SC0 @0x30; /* timer 2 chan 0 status/ctrl */
volatile uint T2CH0 @0x31; /* timer 2 chan 0 register */
volatile char T2CH0H @0x31; /* timer 2 chan 0 high */
volatile char T2CH0L @0x32; /* timer 2 chan 0 low */
volatile char T2SC1 @0x33; /* timer 2 chan 1 status/ctrl */
volatile uint T2CH1 @0x34; /* timer 2 chan 1 register */
volatile char T2CH1H @0x34; /* timer 2 chan 1 high */
volatile char T2CH1L @0x35; /* timer 2 chan 1 low */
/* PLL section
*/
volatile char PCTL @0x36; /* PLL control register */
volatile char PBWC @0x37; /* PLL bandwidth control register*/
volatile uint PMS @0x38; /* PLL multiplier select register */
volatile char PMSH @0x38; /* PLL multiplier select high */
volatile char PMSL @0x39; /* PLL multiplier select low */
volatile char PMRS @0x3a; /* PLL VCO select range register */
volatile char PMDS @0x3b; /* PLL reference divider register */
/* ANALOG/DIGTAL section
*/
volatile char ADSCR @0x3c; /* A/D status/ctrl register */
volatile char ADR @0x3d; /* A/D data register */
volatile char ADCLK @0x3a; /* A/D input clock register */
/* SIM section
*/
volatile char SBSR @0xfe00; /* SIM break status register */
volatile char SRSR @0xfe01; /* SIM reset status register */
volatile char SUBAR @0xfe02; /* SIM upper byte addess register */
volatile char SBFCR @0xfe03; /* SIM break control register */
volatile char INT1 @0xfe04; /* interrupt status register 1 */
volatile char INT2 @0xfe05; /* interrupt status register 2 */
volatile char INT3 @0xfe06; /* interrupt status register 3 */
volatile char FLTCR @0xfe07; /* FLASH test control register */
volatile char FLCR @0xfe08; /* FLASH control register */
volatile uint BRK @0xfe09; /* BREAK address register */
volatile char BRKH @0xfe09; /* BREAK address register low */
volatile char BRKL @0xfe0a; /* BREAK address register high */
volatile char BRKSCR @0xfe0b; /* BREAK status/ctrl register */
volatile char LVISR @0xfe0c; /* LVI status register */
volatile char FLBPR @0xfe80; /* FLASH block protect register */
volatile char COPCTL @0xffff; /* COP control register */
#define cli() _asm("CLI\n"); //Enable interrupts
#define sti() _asm("SEI\n"); //Enable interrupts
#undef uint
#endif