www.pudn.com > ShiftReg4.zip > ShiftReg4.vhd, change:2015-07-10,size:1382b


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-- Company:  
-- Engineer:  
--  
-- Create Date:    12:47:18 07/10/2015  
-- Design Name:  
-- Module Name:    ShiftReg4 - Behavioral  
-- Project Name:  
-- Target Devices:  
-- Tool versions:  
-- Description:  
-- 
-- Dependencies:  
-- 
-- Revision:  
-- Revision 0.01 - File Created 
-- Additional Comments:  
-- 
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library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
 
-- Uncomment the following library declaration if using 
-- arithmetic functions with Signed or Unsigned values 
--use IEEE.NUMERIC_STD.ALL; 
 
-- Uncomment the following library declaration if instantiating 
-- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 
 
entity ShiftReg4 is 
    Port ( A : in  STD_LOGIC;--数据输入 
           clk : in  STD_LOGIC;--时钟信号 
           B : out  STD_LOGIC);--数据输出 
end ShiftReg4; 
 
architecture Behavioral of ShiftReg4 is 
--元件例化 
component DFF 
port(d, CLK: in std_logic; 
		q: out std_logic); 
end component; 
signal x: std_logic_vector(4 downto 0);--用与连接管脚的信号 
begin 
x(0) <= A; 
G1:for i in 0 to 3 generate 
	U1:DFF port map(x(i), clk, x(i+1));--按位置匹配引脚 
end generate; 
B <= x(4);--最后一个D触发器的输出正是数据输出 
 
end Behavioral;