www.pudn.com > ShiftReg4.zip > ShiftReg4.gise, change:2015-07-10,size:5923b
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> <generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> <!-- --> <!-- For tool use only. Do not edit. --> <!-- --> <!-- ProjectNavigator created generated project file. --> <!-- For use in tracking generated file and other information --> <!-- allowing preservation of process status. --> <!-- --> <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version> <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ShiftReg4.xise"/> <files xmlns="http://www.xilinx.com/XMLSchema"> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="DFF_isim_beh.exe"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="DFF_stx_beh.prj"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="DFF_tb_isim_beh.exe"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="DFF_tb_stx_beh.prj"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="ShiftReg4_isim_beh.exe"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ShiftReg4_stx_beh.prj"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ShiftReg4_tb_beh.prj"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="ShiftReg4_tb_isim_beh.exe"/> <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="ShiftReg4_tb_isim_beh.wdb"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ShiftReg4_tb_stx_beh.prj"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ShiftRge4_tb_beh.prj"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="ShiftRge4_tb_isim_beh.exe"/> <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="ShiftRge4_tb_isim_beh.wdb"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ShiftRge4_tb_stx_beh.prj"/> <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> </files> <transforms xmlns="http://www.xilinx.com/XMLSchema"> <transform xil_pn:end_ts="1436504949" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1436504948"> <status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="ReadyToRun"/> </transform> <transform xil_pn:end_ts="1436525346" xil_pn:in_ck="6794989490673167242" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1436525346"> <status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="ReadyToRun"/> <outfile xil_pn:name="DFF.vhd"/> <outfile xil_pn:name="DFF_tb.vhd"/> <outfile xil_pn:name="ShiftReg4.vhd"/> <outfile xil_pn:name="ShiftRge4_tb.vhd"/> </transform> <transform xil_pn:end_ts="1436518050" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-9014527151550399771" xil_pn:start_ts="1436518050"> <status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="ReadyToRun"/> </transform> <transform xil_pn:end_ts="1436518050" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="2012319116097968743" xil_pn:start_ts="1436518050"> <status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="ReadyToRun"/> </transform> <transform xil_pn:end_ts="1436504950" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="1433039399525075358" xil_pn:start_ts="1436504950"> <status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="ReadyToRun"/> </transform> <transform xil_pn:end_ts="1436525346" xil_pn:in_ck="6794989490673167242" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1436525346"> <status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="ReadyToRun"/> <outfile xil_pn:name="DFF.vhd"/> <outfile xil_pn:name="DFF_tb.vhd"/> <outfile xil_pn:name="ShiftReg4.vhd"/> <outfile xil_pn:name="ShiftRge4_tb.vhd"/> </transform> <transform xil_pn:end_ts="1436526480" xil_pn:in_ck="6794989490673167242" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4718095466683149634" xil_pn:start_ts="1436526477"> <status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="ReadyToRun"/> <status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutputChanged"/> <outfile xil_pn:name="ShiftRge4_tb_beh.prj"/> <outfile xil_pn:name="ShiftRge4_tb_isim_beh.exe"/> <outfile xil_pn:name="fuse.log"/> <outfile xil_pn:name="isim"/> <outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="xilinxsim.ini"/> </transform> <transform xil_pn:end_ts="1436526480" xil_pn:in_ck="2805963928198337370" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-3377711601996107291" xil_pn:start_ts="1436526480"> <status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="ReadyToRun"/> <status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutputChanged"/> <outfile xil_pn:name="ShiftRge4_tb_isim_beh.wdb"/> <outfile xil_pn:name="isim.cmd"/> <outfile xil_pn:name="isim.log"/> </transform> </transforms> </generated_project>