www.pudn.com > ShiftReg4.zip > DFF_tb.vhd, change:2015-07-10,size:2044b

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-- Company:  
-- Engineer: 
-- 
-- Create Date:   12:43:13 07/10/2015 
-- Design Name:    
-- Module Name:   D:/ShiftReg4/DFF_tb.vhd 
-- Project Name:  ShiftReg4 
-- Target Device:   
-- Tool versions:   
-- Description:    
--  
-- VHDL Test Bench Created by ISE for module: DFF 
--  
-- Dependencies: 
--  
-- Revision: 
-- Revision 0.01 - File Created 
-- Additional Comments: 
-- 
-- Notes:  
-- This testbench has been automatically generated using types std_logic and 
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation  
-- simulation model. 
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LIBRARY ieee; 
USE ieee.std_logic_1164.ALL; 
  
-- Uncomment the following library declaration if using 
-- arithmetic functions with Signed or Unsigned values 
--USE ieee.numeric_std.ALL; 
  
ENTITY DFF_tb IS 
END DFF_tb; 
  
ARCHITECTURE behavior OF DFF_tb IS  
  
    -- Component Declaration for the Unit Under Test (UUT) 
  
    COMPONENT DFF 
    PORT( 
         d : IN  std_logic; 
         clk : IN  std_logic; 
         q : OUT  std_logic 
        ); 
    END COMPONENT; 
     
 
   --Inputs 
   signal d : std_logic := '0'; 
   signal clk : std_logic := '0'; 
 
 	--Outputs 
   signal q : std_logic; 
 
   -- Clock period definitions 
 
BEGIN 
  
	-- Instantiate the Unit Under Test (UUT) 
   uut: DFF PORT MAP ( 
          d => d, 
          clk => clk, 
          q => q 
        ); 
  
 
   -- Stimulus process 
   stim_proc: process 
   begin		 
      -- hold reset state for 100 ns. 
      wait for 50 ns;	 
		clk <= '0'; 
		d <= '1'; 
		wait for 50 ns; 
		clk <= '1'; 
		wait for 50 ns; 
		clk <= '0'; 
		d <= '0'; 
		wait for 50 ns; 
		clk <= '1'; 
   
      -- insert stimulus here  
 
      wait; 
   end process; 
 
END;