www.pudn.com > ShiftReg4.zip > DFF.vhd, change:2015-07-10,size:1159b

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-- Company:  
-- Engineer:  
--  
-- Create Date:    12:40:42 07/10/2015  
-- Design Name:  
-- Module Name:    DFF - Behavioral  
-- Project Name:  
-- Target Devices:  
-- Tool versions:  
-- Description:  
-- 
-- Dependencies:  
-- 
-- Revision:  
-- Revision 0.01 - File Created 
-- Additional Comments:  
-- 
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library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
 
-- Uncomment the following library declaration if using 
-- arithmetic functions with Signed or Unsigned values 
--use IEEE.NUMERIC_STD.ALL; 
 
-- Uncomment the following library declaration if instantiating 
-- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 
 
entity DFF is 
    Port ( d : in  STD_LOGIC;	--数据输入 
           clk : in  STD_LOGIC; --时钟信号 
           q : out  STD_LOGIC); --数据输出 
end DFF; 
 
architecture Behavioral of DFF is 
 
begin 
process(clk) 
 
begin 
if clk'event and clk='1' then --当上升沿到来，q<=d 
q <= d; 
end if; 
end process; 
 
end Behavioral;