www.pudn.com > SD_Card.rar > dffpipe_b09.tdf, change:2014-06-13,size:1750b

--dffpipe DELAY=2 WIDTH=10 clock d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF 
--VERSION_BEGIN 11.0 cbx_mgl 2011:04:27:21:11:03:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2011 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
 
--synthesis_resources = reg 20  
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF"; 
 
SUBDESIGN dffpipe_b09 
(  
	clock	:	input; 
	d[9..0]	:	input; 
	q[9..0]	:	output; 
)  
VARIABLE  
	dffe19a[9..0] : dffe; 
	dffe20a[9..0] : dffe; 
	clrn	: NODE; 
	ena	: NODE; 
	prn	: NODE; 
	sclr	: NODE; 
 
BEGIN  
	dffe19a[].clk = clock; 
	dffe19a[].clrn = clrn; 
	dffe19a[].d = (d[] & (! sclr)); 
	dffe19a[].ena = ena; 
	dffe19a[].prn = prn; 
	dffe20a[].clk = clock; 
	dffe20a[].clrn = clrn; 
	dffe20a[].d = (dffe19a[].q & (! sclr)); 
	dffe20a[].ena = ena; 
	dffe20a[].prn = prn; 
	clrn = VCC; 
	ena = VCC; 
	prn = VCC; 
	q[] = dffe20a[].q; 
	sclr = GND; 
END; 
--VALID FILE