www.pudn.com > SD_Card.rar > dcfifo_jse1.tdf, change:2014-06-13,size:5243b


--dcfifo_mixed_widths CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=512 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTH_R=8 LPM_WIDTHU=9 LPM_WIDTHU_R=9 OVERFLOW_CHECKING="ON" RDSYNC_DELAYPIPE=4 UNDERFLOW_CHECKING="ON" USE_EAB="ON" WRSYNC_DELAYPIPE=4 data q rdclk rdempty rdreq wrclk wrreq CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone IV E" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF 
--VERSION_BEGIN 11.0 cbx_a_gray2bin 2011:04:27:21:07:19:SJ cbx_a_graycounter 2011:04:27:21:07:19:SJ cbx_altdpram 2011:04:27:21:07:19:SJ cbx_altsyncram 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_dcfifo 2011:04:27:21:07:19:SJ cbx_fifo_common 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_counter 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_scfifo 2011:04:27:21:07:19:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2011 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION a_graycounter_3p6 (clock, cnt_en) 
RETURNS ( q[9..0]); 
FUNCTION a_graycounter_v6c (clock, cnt_en) 
RETURNS ( q[9..0]); 
FUNCTION a_graycounter_u6c (clock, cnt_en) 
RETURNS ( q[9..0]); 
FUNCTION altsyncram_vou (address_a[8..0], address_b[8..0], addressstall_b, clock0, clock1, clocken1, data_a[7..0], wren_a) 
RETURNS ( q_b[7..0]); 
FUNCTION alt_synch_pipe_b7d (clock, d[9..0]) 
RETURNS ( q[9..0]); 
FUNCTION alt_synch_pipe_c7d (clock, d[9..0]) 
RETURNS ( q[9..0]); 
FUNCTION cmpr_n76 (dataa[9..0], datab[9..0]) 
RETURNS ( aeb); 
 
--synthesis_resources = M9K 1 reg 102  
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 2;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe18|dffe19a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_b09:dffpipe18|dffe19a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe15|dffe16a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_a09:dffpipe15|dffe16a* """; 
 
SUBDESIGN dcfifo_jse1 
(  
	data[7..0]	:	input; 
	q[7..0]	:	output; 
	rdclk	:	input; 
	rdempty	:	output; 
	rdreq	:	input; 
	wrclk	:	input; 
	wrreq	:	input; 
)  
VARIABLE  
	rdptr_g1p : a_graycounter_3p6; 
	wrptr_g1p : a_graycounter_v6c; 
	wrptr_gp : a_graycounter_u6c; 
	fifo_ram : altsyncram_vou; 
	delayed_wrptr_g[9..0] : dffe; 
	rdptr_g[9..0] : dffe; 
	rs_dgwp : alt_synch_pipe_b7d; 
	ws_dgrp : alt_synch_pipe_c7d; 
	rdempty_eq_comp : cmpr_n76; 
	wrfull_eq_comp : cmpr_n76; 
	int_rdempty	: WIRE; 
	int_wrfull	: WIRE; 
	ram_address_a[8..0]	: WIRE; 
	ram_address_b[8..0]	: WIRE; 
	valid_rdreq	: WIRE; 
	valid_wrreq	: WIRE; 
	wrptr_gs[9..0]	: WIRE; 
 
BEGIN  
	rdptr_g1p.clock = rdclk; 
	rdptr_g1p.cnt_en = valid_rdreq; 
	wrptr_g1p.clock = wrclk; 
	wrptr_g1p.cnt_en = valid_wrreq; 
	wrptr_gp.clock = wrclk; 
	wrptr_gp.cnt_en = valid_wrreq; 
	fifo_ram.address_a[] = ram_address_a[]; 
	fifo_ram.address_b[] = ram_address_b[]; 
	fifo_ram.addressstall_b = (! valid_rdreq); 
	fifo_ram.clock0 = wrclk; 
	fifo_ram.clock1 = rdclk; 
	fifo_ram.clocken1 = valid_rdreq; 
	fifo_ram.data_a[] = data[]; 
	fifo_ram.wren_a = valid_wrreq; 
	delayed_wrptr_g[].clk = wrclk; 
	delayed_wrptr_g[].d = wrptr_gp.q[]; 
	rdptr_g[].clk = rdclk; 
	rdptr_g[].d = rdptr_g1p.q[]; 
	rdptr_g[].ena = valid_rdreq; 
	rs_dgwp.clock = rdclk; 
	rs_dgwp.d[] = delayed_wrptr_g[].q; 
	ws_dgrp.clock = wrclk; 
	ws_dgrp.d[] = rdptr_g[].q; 
	rdempty_eq_comp.dataa[] = rs_dgwp.q[]; 
	rdempty_eq_comp.datab[] = rdptr_g[].q; 
	wrfull_eq_comp.dataa[] = ws_dgrp.q[]; 
	wrfull_eq_comp.datab[] = wrptr_gs[]; 
	int_rdempty = rdempty_eq_comp.aeb; 
	int_wrfull = wrfull_eq_comp.aeb; 
	q[] = fifo_ram.q_b[]; 
	ram_address_a[] = ( (wrptr_gp.q[9..9] $ wrptr_gp.q[8..8]), wrptr_gp.q[7..0]); 
	ram_address_b[] = ( (rdptr_g1p.q[9..9] $ rdptr_g1p.q[8..8]), rdptr_g1p.q[7..0]); 
	rdempty = int_rdempty; 
	valid_rdreq = (rdreq & (! int_rdempty)); 
	valid_wrreq = (wrreq & (! int_wrfull)); 
	wrptr_gs[] = ( (! wrptr_gp.q[9..9]), (! wrptr_gp.q[8..8]), wrptr_gp.q[7..0]); 
END; 
--VALID FILE