www.pudn.com > SD_Card.rar > alt_synch_pipe_c7d.tdf, change:2014-06-13,size:2146b

--dffpipe DELAY=2 WIDTH=10 clock d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS 
--VERSION_BEGIN 11.0 cbx_a_gray2bin 2011:04:27:21:07:19:SJ cbx_a_graycounter 2011:04:27:21:07:19:SJ cbx_altdpram 2011:04:27:21:07:19:SJ cbx_altsyncram 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_dcfifo 2011:04:27:21:07:19:SJ cbx_fifo_common 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_counter 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_scfifo 2011:04:27:21:07:19:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2011 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION dffpipe_b09 (clock, d[9..0]) 
RETURNS ( q[9..0]); 
 
--synthesis_resources = reg 20  
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS"; 
 
SUBDESIGN alt_synch_pipe_c7d 
(  
	clock	:	input; 
	d[9..0]	:	input; 
	q[9..0]	:	output; 
)  
VARIABLE  
	dffpipe18 : dffpipe_b09; 
 
BEGIN  
	dffpipe18.clock = clock; 
	dffpipe18.d[] = d[]; 
	q[] = dffpipe18.q[]; 
END; 
--VALID FILE