www.pudn.com > SD_Card.rar > SD_Card.lpc.html, change:2014-06-13,size:6528b


<TABLE BORDER="1" cellspacing="1" cellpadding="2"> 
<TR valign="middle" bgcolor="#C0C0C0"> 
<TH>Hierarchy</TH> 
<TH>Input</TH> 
<TH>Constant Input</TH> 
<TH>Unused Input</TH> 
<TH>Floating Input</TH> 
<TH>Output</TH> 
<TH>Constant Output</TH> 
<TH>Unused Output</TH> 
<TH>Floating Output</TH> 
<TH>Bidir</TH> 
<TH>Constant Bidir</TH> 
<TH>Unused Bidir</TH> 
<TH>Input only Bidir</TH> 
<TH>Output only Bidir</TH> 
</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|wrfull_eq_comp</TD> 
<TD ALIGN="LEFT">20</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">1</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|rdempty_eq_comp</TD> 
<TD ALIGN="LEFT">20</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">1</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe18</TD> 
<TD ALIGN="LEFT">11</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">10</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|ws_dgrp</TD> 
<TD ALIGN="LEFT">11</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">10</TD> 
<TD ALIGN="LEFT">0</TD> 
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<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe15</TD> 
<TD ALIGN="LEFT">11</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">10</TD> 
<TD ALIGN="LEFT">0</TD> 
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<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|rs_dgwp</TD> 
<TD ALIGN="LEFT">11</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">10</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|fifo_ram</TD> 
<TD ALIGN="LEFT">31</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">8</TD> 
<TD ALIGN="LEFT">0</TD> 
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</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|wrptr_gp</TD> 
<TD ALIGN="LEFT">2</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
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<TD ALIGN="LEFT">10</TD> 
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<TD ALIGN="LEFT">0</TD> 
</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|wrptr_g1p</TD> 
<TD ALIGN="LEFT">2</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
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</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated|rdptr_g1p</TD> 
<TD ALIGN="LEFT">2</TD> 
<TD ALIGN="LEFT">0</TD> 
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<TD ALIGN="LEFT">10</TD> 
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<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo|dcfifo_component|auto_generated</TD> 
<TD ALIGN="LEFT">12</TD> 
<TD ALIGN="LEFT">0</TD> 
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<TD ALIGN="LEFT">9</TD> 
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</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd|rd_fifo</TD> 
<TD ALIGN="LEFT">12</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">9</TD> 
<TD ALIGN="LEFT">0</TD> 
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</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_sd_spi_secrd</TD> 
<TD ALIGN="LEFT">37</TD> 
<TD ALIGN="LEFT">32</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">32</TD> 
<TD ALIGN="LEFT">3</TD> 
<TD ALIGN="LEFT">32</TD> 
<TD ALIGN="LEFT">32</TD> 
<TD ALIGN="LEFT">32</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
</TR> 
<TR valign="middle"> 
<TD ALIGN="LEFT">uut_init</TD> 
<TD ALIGN="LEFT">3</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">4</TD> 
<TD ALIGN="LEFT">0</TD> 
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<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
<TD ALIGN="LEFT">0</TD> 
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<TD ALIGN="LEFT">0</TD> 
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