www.pudn.com > SD_Card.rar > SD_Card.hif, change:2014-06-13,size:12409b


Quartus II 64-Bit 
Version 11.0 Build 157 04/27/2011 SJ Full Version 
15 
1153 
OFF 
OFF 
OFF 
ON 
ON 
ON 
FV_OFF 
Level2 
0 
0 
VRSM_ON 
VHSM_ON 
0 
-- Start Library Paths -- 
-- End Library Paths -- 
-- Start VHDL Libraries -- 
-- End VHDL Libraries -- 
# entity 
SD_Card 
# storage 
db|SD_Card.(0).cnf 
db|SD_Card.(0).cnf 
# logic_option { 
AUTO_RAM_RECOGNITION 
ON 
} 
# case_sensitive 
# source_file 
sd_card.v 
1543975a44de63d79e9e471d73eb1114 
8 
# internal_option { 
HDL_INITIAL_FANOUT_LIMIT 
OFF 
AUTO_RESOURCE_SHARING 
OFF 
AUTO_RAM_RECOGNITION 
ON 
AUTO_ROM_RECOGNITION 
ON 
IGNORE_VERILOG_INITIAL_CONSTRUCTS 
OFF 
VERILOG_CONSTANT_LOOP_LIMIT 
5000 
VERILOG_NON_CONSTANT_LOOP_LIMIT 
250 
} 
# hierarchies { 
| 
} 
# macro_sequence 
 
# end 
# entity 
sd_spi_init 
# storage 
db|SD_Card.(1).cnf 
db|SD_Card.(1).cnf 
# logic_option { 
AUTO_RAM_RECOGNITION 
ON 
} 
# case_sensitive 
# source_file 
sd_spi_init.v 
9ed25b161adfa92e990376526b8868a 
8 
# internal_option { 
HDL_INITIAL_FANOUT_LIMIT 
OFF 
AUTO_RESOURCE_SHARING 
OFF 
AUTO_RAM_RECOGNITION 
ON 
AUTO_ROM_RECOGNITION 
ON 
IGNORE_VERILOG_INITIAL_CONSTRUCTS 
OFF 
VERILOG_CONSTANT_LOOP_LIMIT 
5000 
VERILOG_NON_CONSTANT_LOOP_LIMIT 
250 
} 
# user_parameter { 
IDLE 
00000 
PARAMETER_UNSIGNED_BIN 
DEF 
CLR_CS 
00001 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD0_0 
00010 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD0_1 
00011 
PARAMETER_UNSIGNED_BIN 
DEF 
RSP_COMD0_0 
00100 
PARAMETER_UNSIGNED_BIN 
DEF 
RSP_COMD0_1 
00101 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD55_0 
00110 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD55_1 
00111 
PARAMETER_UNSIGNED_BIN 
DEF 
RSP_COMD55_0 
01000 
PARAMETER_UNSIGNED_BIN 
DEF 
RSP_COMD55_1 
01001 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD59_0 
01010 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD59_1 
01011 
PARAMETER_UNSIGNED_BIN 
DEF 
WAIT 
01100 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD16_0 
01101 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD16_1 
01110 
PARAMETER_UNSIGNED_BIN 
DEF 
INIT_DONE 
01111 
PARAMETER_UNSIGNED_BIN 
DEF 
WAIT1 
10000 
PARAMETER_UNSIGNED_BIN 
DEF 
WAIT2 
10001 
PARAMETER_UNSIGNED_BIN 
DEF 
ACMD41_0 
10010 
PARAMETER_UNSIGNED_BIN 
DEF 
ACMD41_1 
10011 
PARAMETER_UNSIGNED_BIN 
DEF 
RSP_ACMD41_0 
10100 
PARAMETER_UNSIGNED_BIN 
DEF 
RSP_ACMD41_1 
10101 
PARAMETER_UNSIGNED_BIN 
DEF 
WAIT3 
10110 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD8_0 
10111 
PARAMETER_UNSIGNED_BIN 
DEF 
COMD8_1 
11000 
PARAMETER_UNSIGNED_BIN 
DEF 
RSP_COMD8_0 
11001 
PARAMETER_UNSIGNED_BIN 
DEF 
RSP_COMD8_1 
11010 
PARAMETER_UNSIGNED_BIN 
DEF 
WAIT4 
11011 
PARAMETER_UNSIGNED_BIN 
DEF 
} 
# hierarchies { 
sd_spi_init:uut_init 
} 
# macro_sequence 
 
# end 
# entity 
sd_spi_secrd 
# storage 
db|SD_Card.(2).cnf 
db|SD_Card.(2).cnf 
# logic_option { 
AUTO_RAM_RECOGNITION 
ON 
} 
# case_sensitive 
# source_file 
sd_spi_secrd.v 
89bd19cc11cb9b6c116dcee0681fc237 
8 
# internal_option { 
HDL_INITIAL_FANOUT_LIMIT 
OFF 
AUTO_RESOURCE_SHARING 
OFF 
AUTO_RAM_RECOGNITION 
ON 
AUTO_ROM_RECOGNITION 
ON 
IGNORE_VERILOG_INITIAL_CONSTRUCTS 
OFF 
VERILOG_CONSTANT_LOOP_LIMIT 
5000 
VERILOG_NON_CONSTANT_LOOP_LIMIT 
250 
} 
# user_parameter { 
IDLE 
000 
PARAMETER_UNSIGNED_BIN 
DEF 
BE_CMD 
001 
PARAMETER_UNSIGNED_BIN 
DEF 
SEND_CMD 
010 
PARAMETER_UNSIGNED_BIN 
DEF 
WAIT_RSP 
011 
PARAMETER_UNSIGNED_BIN 
DEF 
CATCH_DATA_ST 
100 
PARAMETER_UNSIGNED_BIN 
DEF 
RCV_DATA 
101 
PARAMETER_UNSIGNED_BIN 
DEF 
RD_DONE 
110 
PARAMETER_UNSIGNED_BIN 
DEF 
RD_ERR 
111 
PARAMETER_UNSIGNED_BIN 
DEF 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd 
} 
# macro_sequence 
 
# end 
# entity 
rw_fifo 
# storage 
db|SD_Card.(3).cnf 
db|SD_Card.(3).cnf 
# logic_option { 
AUTO_RAM_RECOGNITION 
ON 
} 
# case_sensitive 
# source_file 
rw_fifo.v 
46353510a1466b493d9ce8aae4126ee 
8 
# internal_option { 
HDL_INITIAL_FANOUT_LIMIT 
OFF 
AUTO_RESOURCE_SHARING 
OFF 
AUTO_RAM_RECOGNITION 
ON 
AUTO_ROM_RECOGNITION 
ON 
IGNORE_VERILOG_INITIAL_CONSTRUCTS 
OFF 
VERILOG_CONSTANT_LOOP_LIMIT 
5000 
VERILOG_NON_CONSTANT_LOOP_LIMIT 
250 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo 
} 
# macro_sequence 
 
# end 
# entity 
dcfifo 
# storage 
db|SD_Card.(4).cnf 
db|SD_Card.(4).cnf 
# case_insensitive 
# source_file 
|altera|11.0|quartus|libraries|megafunctions|dcfifo.tdf 
27d554629393f1cfc78a2c3ccb14777 
7 
# user_parameter { 
WIDTH_BYTEENA 
1 
PARAMETER_UNKNOWN 
DEF 
AUTO_CARRY_CHAINS 
ON 
AUTO_CARRY 
USR 
IGNORE_CARRY_BUFFERS 
OFF 
IGNORE_CARRY 
USR 
AUTO_CASCADE_CHAINS 
ON 
AUTO_CASCADE 
USR 
IGNORE_CASCADE_BUFFERS 
OFF 
IGNORE_CASCADE 
USR 
LPM_WIDTH 
8 
PARAMETER_SIGNED_DEC 
USR 
LPM_NUMWORDS 
512 
PARAMETER_SIGNED_DEC 
USR 
LPM_WIDTHU 
9 
PARAMETER_SIGNED_DEC 
USR 
LPM_SHOWAHEAD 
OFF 
PARAMETER_UNKNOWN 
USR 
UNDERFLOW_CHECKING 
ON 
PARAMETER_UNKNOWN 
USR 
OVERFLOW_CHECKING 
ON 
PARAMETER_UNKNOWN 
USR 
USE_EAB 
ON 
PARAMETER_UNKNOWN 
USR 
ADD_RAM_OUTPUT_REGISTER 
OFF 
PARAMETER_UNKNOWN 
DEF 
DELAY_RDUSEDW 
1 
PARAMETER_UNKNOWN 
DEF 
DELAY_WRUSEDW 
1 
PARAMETER_UNKNOWN 
DEF 
RDSYNC_DELAYPIPE 
4 
PARAMETER_SIGNED_DEC 
USR 
WRSYNC_DELAYPIPE 
4 
PARAMETER_SIGNED_DEC 
USR 
CLOCKS_ARE_SYNCHRONIZED 
FALSE 
PARAMETER_UNKNOWN 
DEF 
MAXIMIZE_SPEED 
5 
PARAMETER_UNKNOWN 
DEF 
DEVICE_FAMILY 
Cyclone IV E 
PARAMETER_UNKNOWN 
USR 
ADD_USEDW_MSB_BIT 
OFF 
PARAMETER_UNKNOWN 
DEF 
WRITE_ACLR_SYNCH 
OFF 
PARAMETER_UNKNOWN 
DEF 
CBXI_PARAMETER 
dcfifo_jse1 
PARAMETER_UNKNOWN 
USR 
} 
# used_port { 
wrreq 
-1 
3 
wrclk 
-1 
3 
rdreq 
-1 
3 
rdempty 
-1 
3 
rdclk 
-1 
3 
q 
-1 
3 
data 
-1 
3 
} 
# include_file { 
aglobal110.inc 
f560f9a992734abc3e37886b3957a26a 
a_gray2bin.inc 
7e4b761bbeb1a382a47a2f89c3e13e 
alt_sync_fifo.inc 
a019bef5b1e7379dfab915daa2a6c4 
dffpipe.inc 
5471cd80ee441dd293deca0963c9aa0 
lpm_compare.inc 
bbd3e8c93afb7320934629e5fb11566 
altdpram.inc 
2f9e6727b678ffd76e72bc5a95a2630 
lpm_add_sub.inc 
144a73b61081a2a03554ff5acc5e8842 
dcfifo.tdf 
27d554629393f1cfc78a2c3ccb14777 
a_fefifo.inc 
5a44f50e786a1d286adceb22796b9f 
altsyncram_fifo.inc 
4b2b21790828dd59a04a16f08af58b 
a_graycounter.inc 
c8eabdd6f8e7d384595a15fec505aa8 
lpm_counter.inc 
c5cfeeabc5f2ab60b3453f6abbc42b41 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component 
} 
# macro_sequence 
 
# end 
# entity 
dcfifo_jse1 
# storage 
db|SD_Card.(5).cnf 
db|SD_Card.(5).cnf 
# case_insensitive 
# source_file 
db|dcfifo_jse1.tdf 
6e50dbecef0e61dc630aef1533e4d9 
7 
# used_port { 
wrreq 
-1 
3 
wrclk 
-1 
3 
rdreq 
-1 
3 
rdempty 
-1 
3 
rdclk 
-1 
3 
q7 
-1 
3 
q6 
-1 
3 
q5 
-1 
3 
q4 
-1 
3 
q3 
-1 
3 
q2 
-1 
3 
q1 
-1 
3 
q0 
-1 
3 
data7 
-1 
3 
data6 
-1 
3 
data5 
-1 
3 
data4 
-1 
3 
data3 
-1 
3 
data2 
-1 
3 
data1 
-1 
3 
data0 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated 
} 
# macro_sequence 
 
# end 
# entity 
a_graycounter_3p6 
# storage 
db|SD_Card.(6).cnf 
db|SD_Card.(6).cnf 
# case_insensitive 
# source_file 
db|a_graycounter_3p6.tdf 
94ec7ed9f638e9bcf091c015632f86f3 
7 
# used_port { 
q9 
-1 
3 
q8 
-1 
3 
q7 
-1 
3 
q6 
-1 
3 
q5 
-1 
3 
q4 
-1 
3 
q3 
-1 
3 
q2 
-1 
3 
q1 
-1 
3 
q0 
-1 
3 
cnt_en 
-1 
3 
clock 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|a_graycounter_3p6:rdptr_g1p 
} 
# macro_sequence 
 
# end 
# entity 
a_graycounter_v6c 
# storage 
db|SD_Card.(7).cnf 
db|SD_Card.(7).cnf 
# case_insensitive 
# source_file 
db|a_graycounter_v6c.tdf 
d418afba36a22cc33a9b9a5030a5 
7 
# used_port { 
cnt_en 
-1 
3 
clock 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|a_graycounter_v6c:wrptr_g1p 
} 
# macro_sequence 
 
# end 
# entity 
a_graycounter_u6c 
# storage 
db|SD_Card.(8).cnf 
db|SD_Card.(8).cnf 
# case_insensitive 
# source_file 
db|a_graycounter_u6c.tdf 
81a2946cca79efa42c257ce2de66c6 
7 
# used_port { 
q9 
-1 
3 
q8 
-1 
3 
q7 
-1 
3 
q6 
-1 
3 
q5 
-1 
3 
q4 
-1 
3 
q3 
-1 
3 
q2 
-1 
3 
q1 
-1 
3 
q0 
-1 
3 
cnt_en 
-1 
3 
clock 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|a_graycounter_u6c:wrptr_gp 
} 
# macro_sequence 
 
# end 
# entity 
altsyncram_vou 
# storage 
db|SD_Card.(9).cnf 
db|SD_Card.(9).cnf 
# case_insensitive 
# source_file 
db|altsyncram_vou.tdf 
ddd72396637713d809899d016daa87 
7 
# used_port { 
wren_a 
-1 
3 
q_b7 
-1 
3 
q_b6 
-1 
3 
q_b5 
-1 
3 
q_b4 
-1 
3 
q_b3 
-1 
3 
q_b2 
-1 
3 
q_b1 
-1 
3 
q_b0 
-1 
3 
data_a7 
-1 
3 
data_a6 
-1 
3 
data_a5 
-1 
3 
data_a4 
-1 
3 
data_a3 
-1 
3 
data_a2 
-1 
3 
data_a1 
-1 
3 
data_a0 
-1 
3 
clocken1 
-1 
3 
clock1 
-1 
3 
clock0 
-1 
3 
addressstall_b 
-1 
3 
address_b8 
-1 
3 
address_b7 
-1 
3 
address_b6 
-1 
3 
address_b5 
-1 
3 
address_b4 
-1 
3 
address_b3 
-1 
3 
address_b2 
-1 
3 
address_b1 
-1 
3 
address_b0 
-1 
3 
address_a8 
-1 
3 
address_a7 
-1 
3 
address_a6 
-1 
3 
address_a5 
-1 
3 
address_a4 
-1 
3 
address_a3 
-1 
3 
address_a2 
-1 
3 
address_a1 
-1 
3 
address_a0 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|altsyncram_vou:fifo_ram 
} 
# macro_sequence 
 
# end 
# entity 
alt_synch_pipe_b7d 
# storage 
db|SD_Card.(10).cnf 
db|SD_Card.(10).cnf 
# case_insensitive 
# source_file 
db|alt_synch_pipe_b7d.tdf 
fd8fe87a77ee2d48d387213229f2ced9 
7 
# used_port { 
q9 
-1 
3 
q8 
-1 
3 
q7 
-1 
3 
q6 
-1 
3 
q5 
-1 
3 
q4 
-1 
3 
q3 
-1 
3 
q2 
-1 
3 
q1 
-1 
3 
q0 
-1 
3 
d9 
-1 
3 
d8 
-1 
3 
d7 
-1 
3 
d6 
-1 
3 
d5 
-1 
3 
d4 
-1 
3 
d3 
-1 
3 
d2 
-1 
3 
d1 
-1 
3 
d0 
-1 
3 
clock 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|alt_synch_pipe_b7d:rs_dgwp 
} 
# macro_sequence 
 
# end 
# entity 
dffpipe_a09 
# storage 
db|SD_Card.(11).cnf 
db|SD_Card.(11).cnf 
# case_insensitive 
# source_file 
db|dffpipe_a09.tdf 
fd592fa1e1319923baa6ab83e565ad 
7 
# used_port { 
q9 
-1 
3 
q8 
-1 
3 
q7 
-1 
3 
q6 
-1 
3 
q5 
-1 
3 
q4 
-1 
3 
q3 
-1 
3 
q2 
-1 
3 
q1 
-1 
3 
q0 
-1 
3 
d9 
-1 
3 
d8 
-1 
3 
d7 
-1 
3 
d6 
-1 
3 
d5 
-1 
3 
d4 
-1 
3 
d3 
-1 
3 
d2 
-1 
3 
d1 
-1 
3 
d0 
-1 
3 
clock 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|alt_synch_pipe_b7d:rs_dgwp|dffpipe_a09:dffpipe15 
} 
# macro_sequence 
 
# end 
# entity 
alt_synch_pipe_c7d 
# storage 
db|SD_Card.(12).cnf 
db|SD_Card.(12).cnf 
# case_insensitive 
# source_file 
db|alt_synch_pipe_c7d.tdf 
7bb1cd9eb48ae59037c6a8f0ec0d017 
7 
# used_port { 
q9 
-1 
3 
q8 
-1 
3 
q7 
-1 
3 
q6 
-1 
3 
q5 
-1 
3 
q4 
-1 
3 
q3 
-1 
3 
q2 
-1 
3 
q1 
-1 
3 
q0 
-1 
3 
d9 
-1 
3 
d8 
-1 
3 
d7 
-1 
3 
d6 
-1 
3 
d5 
-1 
3 
d4 
-1 
3 
d3 
-1 
3 
d2 
-1 
3 
d1 
-1 
3 
d0 
-1 
3 
clock 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|alt_synch_pipe_c7d:ws_dgrp 
} 
# macro_sequence 
 
# end 
# entity 
dffpipe_b09 
# storage 
db|SD_Card.(13).cnf 
db|SD_Card.(13).cnf 
# case_insensitive 
# source_file 
db|dffpipe_b09.tdf 
ffb315f94dc89ce5ad96caecc83ae0b 
7 
# used_port { 
q9 
-1 
3 
q8 
-1 
3 
q7 
-1 
3 
q6 
-1 
3 
q5 
-1 
3 
q4 
-1 
3 
q3 
-1 
3 
q2 
-1 
3 
q1 
-1 
3 
q0 
-1 
3 
d9 
-1 
3 
d8 
-1 
3 
d7 
-1 
3 
d6 
-1 
3 
d5 
-1 
3 
d4 
-1 
3 
d3 
-1 
3 
d2 
-1 
3 
d1 
-1 
3 
d0 
-1 
3 
clock 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|alt_synch_pipe_c7d:ws_dgrp|dffpipe_b09:dffpipe18 
} 
# macro_sequence 
 
# end 
# entity 
cmpr_n76 
# storage 
db|SD_Card.(14).cnf 
db|SD_Card.(14).cnf 
# case_insensitive 
# source_file 
db|cmpr_n76.tdf 
a0977a3bae4de97a97a533ae6df217e 
7 
# used_port { 
datab9 
-1 
3 
datab8 
-1 
3 
datab7 
-1 
3 
datab6 
-1 
3 
datab5 
-1 
3 
datab4 
-1 
3 
datab3 
-1 
3 
datab2 
-1 
3 
datab1 
-1 
3 
datab0 
-1 
3 
dataa9 
-1 
3 
dataa8 
-1 
3 
dataa7 
-1 
3 
dataa6 
-1 
3 
dataa5 
-1 
3 
dataa4 
-1 
3 
dataa3 
-1 
3 
dataa2 
-1 
3 
dataa1 
-1 
3 
dataa0 
-1 
3 
aeb 
-1 
3 
} 
# hierarchies { 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|cmpr_n76:rdempty_eq_comp 
sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|cmpr_n76:wrfull_eq_comp 
} 
# macro_sequence 
 
# end 
# complete