www.pudn.com > SD_Card.rar > SD_Card.hier_info, change:2014-06-13,size:27452b


|SD_Card 
CLK_50 => led_on.CLK 
CLK_50 => LED[0]~reg0.CLK 
CLK_50 => clk_12mhz.CLK 
CLK_50 => cnt[0].CLK 
CLK_50 => cnt[1].CLK 
CLK_50 => cnt[2].CLK 
CLK_50 => clk_25mhz.CLK 
KEY[4] => KEY[4].IN2 
SD_DO => SD_DO.IN2 
 
 
|SD_Card|sd_spi_init:uut_init 
clk => cmd_cnt[0].CLK 
clk => cmd_cnt[1].CLK 
clk => cmd_cnt[2].CLK 
clk => cmd_cnt[3].CLK 
clk => cmd_cnt[4].CLK 
clk => cmd_cnt[5].CLK 
clk => rsp_r[0].CLK 
clk => rsp_r[1].CLK 
clk => rsp_r[2].CLK 
clk => rsp_r[3].CLK 
clk => rsp_r[4].CLK 
clk => rsp_r[5].CLK 
clk => rsp_r[6].CLK 
clk => rsp_r[7].CLK 
clk => cmd_r[0].CLK 
clk => cmd_r[1].CLK 
clk => cmd_r[2].CLK 
clk => cmd_r[3].CLK 
clk => cmd_r[4].CLK 
clk => cmd_r[5].CLK 
clk => cmd_r[6].CLK 
clk => cmd_r[7].CLK 
clk => cmd_r[8].CLK 
clk => cmd_r[9].CLK 
clk => cmd_r[10].CLK 
clk => cmd_r[11].CLK 
clk => cmd_r[12].CLK 
clk => cmd_r[13].CLK 
clk => cmd_r[14].CLK 
clk => cmd_r[15].CLK 
clk => cmd_r[16].CLK 
clk => cmd_r[17].CLK 
clk => cmd_r[18].CLK 
clk => cmd_r[19].CLK 
clk => cmd_r[20].CLK 
clk => cmd_r[21].CLK 
clk => cmd_r[22].CLK 
clk => cmd_r[23].CLK 
clk => cmd_r[24].CLK 
clk => cmd_r[25].CLK 
clk => cmd_r[26].CLK 
clk => cmd_r[27].CLK 
clk => cmd_r[28].CLK 
clk => cmd_r[29].CLK 
clk => cmd_r[30].CLK 
clk => cmd_r[31].CLK 
clk => cmd_r[32].CLK 
clk => cmd_r[33].CLK 
clk => cmd_r[34].CLK 
clk => cmd_r[35].CLK 
clk => cmd_r[36].CLK 
clk => cmd_r[37].CLK 
clk => cmd_r[38].CLK 
clk => cmd_r[39].CLK 
clk => cmd_r[40].CLK 
clk => cmd_r[41].CLK 
clk => cmd_r[42].CLK 
clk => cmd_r[43].CLK 
clk => cmd_r[44].CLK 
clk => cmd_r[45].CLK 
clk => cmd_r[46].CLK 
clk => cmd_r[47].CLK 
clk => init_done~reg0.CLK 
clk => st_256.CLK 
clk => scl~reg0.CLK 
clk => cs_n~reg0.CLK 
clk => mosi~reg0.CLK 
clk => cnt_256[0].CLK 
clk => cnt_256[1].CLK 
clk => cnt_256[2].CLK 
clk => cnt_256[3].CLK 
clk => cnt_256[4].CLK 
clk => cnt_256[5].CLK 
clk => cnt_256[6].CLK 
clk => cnt_256[7].CLK 
clk => state~1.DATAIN 
rst_n => Selector8.IN4 
rst_n => cmd_cnt[0].ACLR 
rst_n => cmd_cnt[1].ACLR 
rst_n => cmd_cnt[2].ACLR 
rst_n => cmd_cnt[3].ACLR 
rst_n => cmd_cnt[4].ACLR 
rst_n => cmd_cnt[5].ACLR 
rst_n => rsp_r[0].PRESET 
rst_n => rsp_r[1].PRESET 
rst_n => rsp_r[2].PRESET 
rst_n => rsp_r[3].PRESET 
rst_n => rsp_r[4].PRESET 
rst_n => rsp_r[5].PRESET 
rst_n => rsp_r[6].PRESET 
rst_n => rsp_r[7].PRESET 
rst_n => cmd_r[0].ACLR 
rst_n => cmd_r[1].ACLR 
rst_n => cmd_r[2].ACLR 
rst_n => cmd_r[3].ACLR 
rst_n => cmd_r[4].ACLR 
rst_n => cmd_r[5].ACLR 
rst_n => cmd_r[6].ACLR 
rst_n => cmd_r[7].ACLR 
rst_n => cmd_r[8].ACLR 
rst_n => cmd_r[9].ACLR 
rst_n => cmd_r[10].ACLR 
rst_n => cmd_r[11].ACLR 
rst_n => cmd_r[12].ACLR 
rst_n => cmd_r[13].ACLR 
rst_n => cmd_r[14].ACLR 
rst_n => cmd_r[15].ACLR 
rst_n => cmd_r[16].ACLR 
rst_n => cmd_r[17].ACLR 
rst_n => cmd_r[18].ACLR 
rst_n => cmd_r[19].ACLR 
rst_n => cmd_r[20].ACLR 
rst_n => cmd_r[21].ACLR 
rst_n => cmd_r[22].ACLR 
rst_n => cmd_r[23].ACLR 
rst_n => cmd_r[24].ACLR 
rst_n => cmd_r[25].ACLR 
rst_n => cmd_r[26].ACLR 
rst_n => cmd_r[27].ACLR 
rst_n => cmd_r[28].ACLR 
rst_n => cmd_r[29].ACLR 
rst_n => cmd_r[30].ACLR 
rst_n => cmd_r[31].ACLR 
rst_n => cmd_r[32].ACLR 
rst_n => cmd_r[33].ACLR 
rst_n => cmd_r[34].ACLR 
rst_n => cmd_r[35].ACLR 
rst_n => cmd_r[36].ACLR 
rst_n => cmd_r[37].ACLR 
rst_n => cmd_r[38].ACLR 
rst_n => cmd_r[39].ACLR 
rst_n => cmd_r[40].ACLR 
rst_n => cmd_r[41].ACLR 
rst_n => cmd_r[42].ACLR 
rst_n => cmd_r[43].ACLR 
rst_n => cmd_r[44].ACLR 
rst_n => cmd_r[45].ACLR 
rst_n => cmd_r[46].ACLR 
rst_n => cmd_r[47].ACLR 
rst_n => init_done~reg0.ACLR 
rst_n => st_256.ACLR 
rst_n => scl~reg0.ACLR 
rst_n => cs_n~reg0.PRESET 
rst_n => mosi~reg0.PRESET 
rst_n => cnt_256[0].ACLR 
rst_n => cnt_256[1].ACLR 
rst_n => cnt_256[2].ACLR 
rst_n => cnt_256[3].ACLR 
rst_n => cnt_256[4].ACLR 
rst_n => cnt_256[5].ACLR 
rst_n => cnt_256[6].ACLR 
rst_n => cnt_256[7].ACLR 
rst_n => Selector0.IN1 
rst_n => state~3.DATAIN 
miso => rsp_r.DATAB 
miso => Selector77.IN5 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd 
clk => bit_cnt[0].CLK 
clk => bit_cnt[1].CLK 
clk => bit_cnt[2].CLK 
clk => data_cnt[0].CLK 
clk => data_cnt[1].CLK 
clk => data_cnt[2].CLK 
clk => data_cnt[3].CLK 
clk => data_cnt[4].CLK 
clk => data_cnt[5].CLK 
clk => data_cnt[6].CLK 
clk => data_cnt[7].CLK 
clk => data_cnt[8].CLK 
clk => data_cnt[9].CLK 
clk => data_r[0].CLK 
clk => data_r[1].CLK 
clk => data_r[2].CLK 
clk => data_r[3].CLK 
clk => data_r[4].CLK 
clk => data_r[5].CLK 
clk => data_r[6].CLK 
clk => data_r[7].CLK 
clk => rsp_r[0].CLK 
clk => rsp_r[1].CLK 
clk => rsp_r[2].CLK 
clk => rsp_r[3].CLK 
clk => rsp_r[4].CLK 
clk => rsp_r[5].CLK 
clk => rsp_r[6].CLK 
clk => rsp_r[7].CLK 
clk => cmd_cnt[0].CLK 
clk => cmd_cnt[1].CLK 
clk => cmd_cnt[2].CLK 
clk => cmd_cnt[3].CLK 
clk => cmd_cnt[4].CLK 
clk => cmd_cnt[5].CLK 
clk => cmd_r[0].CLK 
clk => cmd_r[1].CLK 
clk => cmd_r[2].CLK 
clk => cmd_r[3].CLK 
clk => cmd_r[4].CLK 
clk => cmd_r[5].CLK 
clk => cmd_r[6].CLK 
clk => cmd_r[7].CLK 
clk => cmd_r[8].CLK 
clk => cmd_r[9].CLK 
clk => cmd_r[10].CLK 
clk => cmd_r[11].CLK 
clk => cmd_r[12].CLK 
clk => cmd_r[13].CLK 
clk => cmd_r[14].CLK 
clk => cmd_r[15].CLK 
clk => cmd_r[16].CLK 
clk => cmd_r[17].CLK 
clk => cmd_r[18].CLK 
clk => cmd_r[19].CLK 
clk => cmd_r[20].CLK 
clk => cmd_r[21].CLK 
clk => cmd_r[22].CLK 
clk => cmd_r[23].CLK 
clk => cmd_r[24].CLK 
clk => cmd_r[25].CLK 
clk => cmd_r[26].CLK 
clk => cmd_r[27].CLK 
clk => cmd_r[28].CLK 
clk => cmd_r[29].CLK 
clk => cmd_r[30].CLK 
clk => cmd_r[31].CLK 
clk => cmd_r[32].CLK 
clk => cmd_r[33].CLK 
clk => cmd_r[34].CLK 
clk => cmd_r[35].CLK 
clk => cmd_r[36].CLK 
clk => cmd_r[37].CLK 
clk => cmd_r[38].CLK 
clk => cmd_r[39].CLK 
clk => cmd_r[40].CLK 
clk => cmd_r[41].CLK 
clk => cmd_r[42].CLK 
clk => cmd_r[43].CLK 
clk => cmd_r[44].CLK 
clk => cmd_r[45].CLK 
clk => cmd_r[46].CLK 
clk => cmd_r[47].CLK 
clk => rdf_wrreq.CLK 
clk => rdf_data_in[0].CLK 
clk => rdf_data_in[1].CLK 
clk => rdf_data_in[2].CLK 
clk => rdf_data_in[3].CLK 
clk => rdf_data_in[4].CLK 
clk => rdf_data_in[5].CLK 
clk => rdf_data_in[6].CLK 
clk => rdf_data_in[7].CLK 
clk => scl~reg0.CLK 
clk => cs_n~reg0.CLK 
clk => mosi~reg0.CLK 
clk => rd_done~reg0.CLK 
clk => rd_err~reg0.CLK 
clk => st_256.CLK 
clk => cnt_256[0].CLK 
clk => cnt_256[1].CLK 
clk => cnt_256[2].CLK 
clk => cnt_256[3].CLK 
clk => cnt_256[4].CLK 
clk => cnt_256[5].CLK 
clk => cnt_256[6].CLK 
clk => cnt_256[7].CLK 
clk => state~1.DATAIN 
rst_n => Selector103.IN2 
rst_n => bit_cnt[0].ACLR 
rst_n => bit_cnt[1].ACLR 
rst_n => bit_cnt[2].ACLR 
rst_n => data_cnt[0].ACLR 
rst_n => data_cnt[1].ACLR 
rst_n => data_cnt[2].ACLR 
rst_n => data_cnt[3].ACLR 
rst_n => data_cnt[4].ACLR 
rst_n => data_cnt[5].ACLR 
rst_n => data_cnt[6].ACLR 
rst_n => data_cnt[7].ACLR 
rst_n => data_cnt[8].ACLR 
rst_n => data_cnt[9].ACLR 
rst_n => data_r[0].PRESET 
rst_n => data_r[1].PRESET 
rst_n => data_r[2].PRESET 
rst_n => data_r[3].PRESET 
rst_n => data_r[4].PRESET 
rst_n => data_r[5].PRESET 
rst_n => data_r[6].PRESET 
rst_n => data_r[7].PRESET 
rst_n => rsp_r[0].PRESET 
rst_n => rsp_r[1].PRESET 
rst_n => rsp_r[2].PRESET 
rst_n => rsp_r[3].PRESET 
rst_n => rsp_r[4].PRESET 
rst_n => rsp_r[5].PRESET 
rst_n => rsp_r[6].PRESET 
rst_n => rsp_r[7].PRESET 
rst_n => cmd_cnt[0].ACLR 
rst_n => cmd_cnt[1].ACLR 
rst_n => cmd_cnt[2].ACLR 
rst_n => cmd_cnt[3].ACLR 
rst_n => cmd_cnt[4].ACLR 
rst_n => cmd_cnt[5].ACLR 
rst_n => cmd_r[0].ACLR 
rst_n => cmd_r[1].ACLR 
rst_n => cmd_r[2].ACLR 
rst_n => cmd_r[3].ACLR 
rst_n => cmd_r[4].ACLR 
rst_n => cmd_r[5].ACLR 
rst_n => cmd_r[6].ACLR 
rst_n => cmd_r[7].ACLR 
rst_n => cmd_r[8].ACLR 
rst_n => cmd_r[9].ACLR 
rst_n => cmd_r[10].ACLR 
rst_n => cmd_r[11].ACLR 
rst_n => cmd_r[12].ACLR 
rst_n => cmd_r[13].ACLR 
rst_n => cmd_r[14].ACLR 
rst_n => cmd_r[15].ACLR 
rst_n => cmd_r[16].ACLR 
rst_n => cmd_r[17].ACLR 
rst_n => cmd_r[18].ACLR 
rst_n => cmd_r[19].ACLR 
rst_n => cmd_r[20].ACLR 
rst_n => cmd_r[21].ACLR 
rst_n => cmd_r[22].ACLR 
rst_n => cmd_r[23].ACLR 
rst_n => cmd_r[24].ACLR 
rst_n => cmd_r[25].ACLR 
rst_n => cmd_r[26].ACLR 
rst_n => cmd_r[27].ACLR 
rst_n => cmd_r[28].ACLR 
rst_n => cmd_r[29].ACLR 
rst_n => cmd_r[30].ACLR 
rst_n => cmd_r[31].ACLR 
rst_n => cmd_r[32].ACLR 
rst_n => cmd_r[33].ACLR 
rst_n => cmd_r[34].ACLR 
rst_n => cmd_r[35].ACLR 
rst_n => cmd_r[36].ACLR 
rst_n => cmd_r[37].ACLR 
rst_n => cmd_r[38].ACLR 
rst_n => cmd_r[39].ACLR 
rst_n => cmd_r[40].ACLR 
rst_n => cmd_r[41].ACLR 
rst_n => cmd_r[42].ACLR 
rst_n => cmd_r[43].ACLR 
rst_n => cmd_r[44].ACLR 
rst_n => cmd_r[45].ACLR 
rst_n => cmd_r[46].ACLR 
rst_n => cmd_r[47].ACLR 
rst_n => rdf_wrreq.ACLR 
rst_n => rdf_data_in[0].ACLR 
rst_n => rdf_data_in[1].ACLR 
rst_n => rdf_data_in[2].ACLR 
rst_n => rdf_data_in[3].ACLR 
rst_n => rdf_data_in[4].ACLR 
rst_n => rdf_data_in[5].ACLR 
rst_n => rdf_data_in[6].ACLR 
rst_n => rdf_data_in[7].ACLR 
rst_n => scl~reg0.ACLR 
rst_n => cs_n~reg0.PRESET 
rst_n => mosi~reg0.PRESET 
rst_n => rd_done~reg0.ACLR 
rst_n => rd_err~reg0.ACLR 
rst_n => st_256.ACLR 
rst_n => cnt_256[0].ACLR 
rst_n => cnt_256[1].ACLR 
rst_n => cnt_256[2].ACLR 
rst_n => cnt_256[3].ACLR 
rst_n => cnt_256[4].ACLR 
rst_n => cnt_256[5].ACLR 
rst_n => cnt_256[6].ACLR 
rst_n => cnt_256[7].ACLR 
rst_n => Selector96.IN1 
rst_n => tri_state.ACLR 
rst_n => triger.ACLR 
rst_n => state~3.DATAIN 
sec_num[0] => Selector52.IN4 
sec_num[1] => Selector51.IN4 
sec_num[2] => Selector50.IN4 
sec_num[3] => Selector49.IN4 
sec_num[4] => Selector48.IN4 
sec_num[5] => Selector47.IN4 
sec_num[6] => Selector46.IN4 
sec_num[7] => Selector45.IN4 
sec_num[8] => Selector44.IN4 
sec_num[9] => Selector43.IN4 
sec_num[10] => Selector42.IN4 
sec_num[11] => Selector41.IN4 
sec_num[12] => Selector40.IN4 
sec_num[13] => Selector39.IN4 
sec_num[14] => Selector38.IN4 
sec_num[15] => Selector37.IN4 
sec_num[16] => Selector36.IN4 
sec_num[17] => Selector35.IN4 
sec_num[18] => Selector34.IN4 
sec_num[19] => Selector33.IN4 
sec_num[20] => Selector32.IN4 
sec_num[21] => Selector31.IN4 
sec_num[22] => Selector30.IN4 
sec_num[23] => Selector29.IN4 
sec_num[24] => Selector28.IN4 
sec_num[25] => Selector27.IN4 
sec_num[26] => Selector26.IN4 
sec_num[27] => Selector25.IN4 
sec_num[28] => Selector24.IN4 
sec_num[29] => Selector23.IN4 
sec_num[30] => Selector22.IN4 
sec_num[31] => Selector21.IN4 
read_st => Selector97.IN3 
read_st => Selector96.IN2 
miso => rsp_r.DATAB 
miso => data_r.DATAB 
rdf_rdreq => rdf_rdreq.IN1 
rdf_clk => rdf_clk.IN1 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo 
data[0] => data[0].IN1 
data[1] => data[1].IN1 
data[2] => data[2].IN1 
data[3] => data[3].IN1 
data[4] => data[4].IN1 
data[5] => data[5].IN1 
data[6] => data[6].IN1 
data[7] => data[7].IN1 
rdclk => rdclk.IN1 
rdreq => rdreq.IN1 
wrclk => wrclk.IN1 
wrreq => wrreq.IN1 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component 
data[0] => dcfifo_jse1:auto_generated.data[0] 
data[1] => dcfifo_jse1:auto_generated.data[1] 
data[2] => dcfifo_jse1:auto_generated.data[2] 
data[3] => dcfifo_jse1:auto_generated.data[3] 
data[4] => dcfifo_jse1:auto_generated.data[4] 
data[5] => dcfifo_jse1:auto_generated.data[5] 
data[6] => dcfifo_jse1:auto_generated.data[6] 
data[7] => dcfifo_jse1:auto_generated.data[7] 
rdclk => dcfifo_jse1:auto_generated.rdclk 
rdreq => dcfifo_jse1:auto_generated.rdreq 
wrclk => dcfifo_jse1:auto_generated.wrclk 
wrreq => dcfifo_jse1:auto_generated.wrreq 
aclr => ~NO_FANOUT~ 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated 
data[0] => altsyncram_vou:fifo_ram.data_a[0] 
data[1] => altsyncram_vou:fifo_ram.data_a[1] 
data[2] => altsyncram_vou:fifo_ram.data_a[2] 
data[3] => altsyncram_vou:fifo_ram.data_a[3] 
data[4] => altsyncram_vou:fifo_ram.data_a[4] 
data[5] => altsyncram_vou:fifo_ram.data_a[5] 
data[6] => altsyncram_vou:fifo_ram.data_a[6] 
data[7] => altsyncram_vou:fifo_ram.data_a[7] 
rdclk => a_graycounter_3p6:rdptr_g1p.clock 
rdclk => altsyncram_vou:fifo_ram.clock1 
rdclk => alt_synch_pipe_b7d:rs_dgwp.clock 
rdclk => rdptr_g[9].CLK 
rdclk => rdptr_g[8].CLK 
rdclk => rdptr_g[7].CLK 
rdclk => rdptr_g[6].CLK 
rdclk => rdptr_g[5].CLK 
rdclk => rdptr_g[4].CLK 
rdclk => rdptr_g[3].CLK 
rdclk => rdptr_g[2].CLK 
rdclk => rdptr_g[1].CLK 
rdclk => rdptr_g[0].CLK 
rdreq => valid_rdreq.IN0 
wrclk => a_graycounter_v6c:wrptr_g1p.clock 
wrclk => a_graycounter_u6c:wrptr_gp.clock 
wrclk => altsyncram_vou:fifo_ram.clock0 
wrclk => alt_synch_pipe_c7d:ws_dgrp.clock 
wrclk => delayed_wrptr_g[9].CLK 
wrclk => delayed_wrptr_g[8].CLK 
wrclk => delayed_wrptr_g[7].CLK 
wrclk => delayed_wrptr_g[6].CLK 
wrclk => delayed_wrptr_g[5].CLK 
wrclk => delayed_wrptr_g[4].CLK 
wrclk => delayed_wrptr_g[3].CLK 
wrclk => delayed_wrptr_g[2].CLK 
wrclk => delayed_wrptr_g[1].CLK 
wrclk => delayed_wrptr_g[0].CLK 
wrreq => valid_wrreq.IN0 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|a_graycounter_3p6:rdptr_g1p 
clock => counter5a0.CLK 
clock => counter5a1.CLK 
clock => counter5a2.CLK 
clock => counter5a3.CLK 
clock => counter5a4.CLK 
clock => counter5a5.CLK 
clock => counter5a6.CLK 
clock => counter5a7.CLK 
clock => counter5a8.CLK 
clock => counter5a9.CLK 
clock => parity6.CLK 
clock => sub_parity7a[2].CLK 
clock => sub_parity7a[1].CLK 
clock => sub_parity7a[0].CLK 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => cntr_cout[0].IN0 
cnt_en => parity_cout.IN1 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|a_graycounter_v6c:wrptr_g1p 
clock => counter8a0.CLK 
clock => counter8a1.CLK 
clock => counter8a2.CLK 
clock => counter8a3.CLK 
clock => counter8a4.CLK 
clock => counter8a5.CLK 
clock => counter8a6.CLK 
clock => counter8a7.CLK 
clock => counter8a8.CLK 
clock => counter8a9.CLK 
clock => parity9.CLK 
clock => sub_parity10a[2].CLK 
clock => sub_parity10a[1].CLK 
clock => sub_parity10a[0].CLK 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => cntr_cout[0].IN0 
cnt_en => parity_cout.IN1 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|a_graycounter_u6c:wrptr_gp 
clock => counter13a[9].CLK 
clock => counter13a[8].CLK 
clock => counter13a[7].CLK 
clock => counter13a[6].CLK 
clock => counter13a[5].CLK 
clock => counter13a[4].CLK 
clock => counter13a[3].CLK 
clock => counter13a[2].CLK 
clock => counter13a[1].CLK 
clock => counter13a[0].CLK 
clock => parity11.CLK 
clock => sub_parity12a0.CLK 
clock => sub_parity12a1.CLK 
clock => sub_parity12a2.CLK 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => _.IN0 
cnt_en => cntr_cout[0].IN0 
cnt_en => parity_cout.IN1 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|altsyncram_vou:fifo_ram 
address_a[0] => ram_block14a0.PORTAADDR 
address_a[0] => ram_block14a1.PORTAADDR 
address_a[0] => ram_block14a2.PORTAADDR 
address_a[0] => ram_block14a3.PORTAADDR 
address_a[0] => ram_block14a4.PORTAADDR 
address_a[0] => ram_block14a5.PORTAADDR 
address_a[0] => ram_block14a6.PORTAADDR 
address_a[0] => ram_block14a7.PORTAADDR 
address_a[1] => ram_block14a0.PORTAADDR1 
address_a[1] => ram_block14a1.PORTAADDR1 
address_a[1] => ram_block14a2.PORTAADDR1 
address_a[1] => ram_block14a3.PORTAADDR1 
address_a[1] => ram_block14a4.PORTAADDR1 
address_a[1] => ram_block14a5.PORTAADDR1 
address_a[1] => ram_block14a6.PORTAADDR1 
address_a[1] => ram_block14a7.PORTAADDR1 
address_a[2] => ram_block14a0.PORTAADDR2 
address_a[2] => ram_block14a1.PORTAADDR2 
address_a[2] => ram_block14a2.PORTAADDR2 
address_a[2] => ram_block14a3.PORTAADDR2 
address_a[2] => ram_block14a4.PORTAADDR2 
address_a[2] => ram_block14a5.PORTAADDR2 
address_a[2] => ram_block14a6.PORTAADDR2 
address_a[2] => ram_block14a7.PORTAADDR2 
address_a[3] => ram_block14a0.PORTAADDR3 
address_a[3] => ram_block14a1.PORTAADDR3 
address_a[3] => ram_block14a2.PORTAADDR3 
address_a[3] => ram_block14a3.PORTAADDR3 
address_a[3] => ram_block14a4.PORTAADDR3 
address_a[3] => ram_block14a5.PORTAADDR3 
address_a[3] => ram_block14a6.PORTAADDR3 
address_a[3] => ram_block14a7.PORTAADDR3 
address_a[4] => ram_block14a0.PORTAADDR4 
address_a[4] => ram_block14a1.PORTAADDR4 
address_a[4] => ram_block14a2.PORTAADDR4 
address_a[4] => ram_block14a3.PORTAADDR4 
address_a[4] => ram_block14a4.PORTAADDR4 
address_a[4] => ram_block14a5.PORTAADDR4 
address_a[4] => ram_block14a6.PORTAADDR4 
address_a[4] => ram_block14a7.PORTAADDR4 
address_a[5] => ram_block14a0.PORTAADDR5 
address_a[5] => ram_block14a1.PORTAADDR5 
address_a[5] => ram_block14a2.PORTAADDR5 
address_a[5] => ram_block14a3.PORTAADDR5 
address_a[5] => ram_block14a4.PORTAADDR5 
address_a[5] => ram_block14a5.PORTAADDR5 
address_a[5] => ram_block14a6.PORTAADDR5 
address_a[5] => ram_block14a7.PORTAADDR5 
address_a[6] => ram_block14a0.PORTAADDR6 
address_a[6] => ram_block14a1.PORTAADDR6 
address_a[6] => ram_block14a2.PORTAADDR6 
address_a[6] => ram_block14a3.PORTAADDR6 
address_a[6] => ram_block14a4.PORTAADDR6 
address_a[6] => ram_block14a5.PORTAADDR6 
address_a[6] => ram_block14a6.PORTAADDR6 
address_a[6] => ram_block14a7.PORTAADDR6 
address_a[7] => ram_block14a0.PORTAADDR7 
address_a[7] => ram_block14a1.PORTAADDR7 
address_a[7] => ram_block14a2.PORTAADDR7 
address_a[7] => ram_block14a3.PORTAADDR7 
address_a[7] => ram_block14a4.PORTAADDR7 
address_a[7] => ram_block14a5.PORTAADDR7 
address_a[7] => ram_block14a6.PORTAADDR7 
address_a[7] => ram_block14a7.PORTAADDR7 
address_a[8] => ram_block14a0.PORTAADDR8 
address_a[8] => ram_block14a1.PORTAADDR8 
address_a[8] => ram_block14a2.PORTAADDR8 
address_a[8] => ram_block14a3.PORTAADDR8 
address_a[8] => ram_block14a4.PORTAADDR8 
address_a[8] => ram_block14a5.PORTAADDR8 
address_a[8] => ram_block14a6.PORTAADDR8 
address_a[8] => ram_block14a7.PORTAADDR8 
address_b[0] => ram_block14a0.PORTBADDR 
address_b[0] => ram_block14a1.PORTBADDR 
address_b[0] => ram_block14a2.PORTBADDR 
address_b[0] => ram_block14a3.PORTBADDR 
address_b[0] => ram_block14a4.PORTBADDR 
address_b[0] => ram_block14a5.PORTBADDR 
address_b[0] => ram_block14a6.PORTBADDR 
address_b[0] => ram_block14a7.PORTBADDR 
address_b[1] => ram_block14a0.PORTBADDR1 
address_b[1] => ram_block14a1.PORTBADDR1 
address_b[1] => ram_block14a2.PORTBADDR1 
address_b[1] => ram_block14a3.PORTBADDR1 
address_b[1] => ram_block14a4.PORTBADDR1 
address_b[1] => ram_block14a5.PORTBADDR1 
address_b[1] => ram_block14a6.PORTBADDR1 
address_b[1] => ram_block14a7.PORTBADDR1 
address_b[2] => ram_block14a0.PORTBADDR2 
address_b[2] => ram_block14a1.PORTBADDR2 
address_b[2] => ram_block14a2.PORTBADDR2 
address_b[2] => ram_block14a3.PORTBADDR2 
address_b[2] => ram_block14a4.PORTBADDR2 
address_b[2] => ram_block14a5.PORTBADDR2 
address_b[2] => ram_block14a6.PORTBADDR2 
address_b[2] => ram_block14a7.PORTBADDR2 
address_b[3] => ram_block14a0.PORTBADDR3 
address_b[3] => ram_block14a1.PORTBADDR3 
address_b[3] => ram_block14a2.PORTBADDR3 
address_b[3] => ram_block14a3.PORTBADDR3 
address_b[3] => ram_block14a4.PORTBADDR3 
address_b[3] => ram_block14a5.PORTBADDR3 
address_b[3] => ram_block14a6.PORTBADDR3 
address_b[3] => ram_block14a7.PORTBADDR3 
address_b[4] => ram_block14a0.PORTBADDR4 
address_b[4] => ram_block14a1.PORTBADDR4 
address_b[4] => ram_block14a2.PORTBADDR4 
address_b[4] => ram_block14a3.PORTBADDR4 
address_b[4] => ram_block14a4.PORTBADDR4 
address_b[4] => ram_block14a5.PORTBADDR4 
address_b[4] => ram_block14a6.PORTBADDR4 
address_b[4] => ram_block14a7.PORTBADDR4 
address_b[5] => ram_block14a0.PORTBADDR5 
address_b[5] => ram_block14a1.PORTBADDR5 
address_b[5] => ram_block14a2.PORTBADDR5 
address_b[5] => ram_block14a3.PORTBADDR5 
address_b[5] => ram_block14a4.PORTBADDR5 
address_b[5] => ram_block14a5.PORTBADDR5 
address_b[5] => ram_block14a6.PORTBADDR5 
address_b[5] => ram_block14a7.PORTBADDR5 
address_b[6] => ram_block14a0.PORTBADDR6 
address_b[6] => ram_block14a1.PORTBADDR6 
address_b[6] => ram_block14a2.PORTBADDR6 
address_b[6] => ram_block14a3.PORTBADDR6 
address_b[6] => ram_block14a4.PORTBADDR6 
address_b[6] => ram_block14a5.PORTBADDR6 
address_b[6] => ram_block14a6.PORTBADDR6 
address_b[6] => ram_block14a7.PORTBADDR6 
address_b[7] => ram_block14a0.PORTBADDR7 
address_b[7] => ram_block14a1.PORTBADDR7 
address_b[7] => ram_block14a2.PORTBADDR7 
address_b[7] => ram_block14a3.PORTBADDR7 
address_b[7] => ram_block14a4.PORTBADDR7 
address_b[7] => ram_block14a5.PORTBADDR7 
address_b[7] => ram_block14a6.PORTBADDR7 
address_b[7] => ram_block14a7.PORTBADDR7 
address_b[8] => ram_block14a0.PORTBADDR8 
address_b[8] => ram_block14a1.PORTBADDR8 
address_b[8] => ram_block14a2.PORTBADDR8 
address_b[8] => ram_block14a3.PORTBADDR8 
address_b[8] => ram_block14a4.PORTBADDR8 
address_b[8] => ram_block14a5.PORTBADDR8 
address_b[8] => ram_block14a6.PORTBADDR8 
address_b[8] => ram_block14a7.PORTBADDR8 
addressstall_b => ram_block14a0.PORTBADDRSTALL 
addressstall_b => ram_block14a1.PORTBADDRSTALL 
addressstall_b => ram_block14a2.PORTBADDRSTALL 
addressstall_b => ram_block14a3.PORTBADDRSTALL 
addressstall_b => ram_block14a4.PORTBADDRSTALL 
addressstall_b => ram_block14a5.PORTBADDRSTALL 
addressstall_b => ram_block14a6.PORTBADDRSTALL 
addressstall_b => ram_block14a7.PORTBADDRSTALL 
clock0 => ram_block14a0.CLK0 
clock0 => ram_block14a1.CLK0 
clock0 => ram_block14a2.CLK0 
clock0 => ram_block14a3.CLK0 
clock0 => ram_block14a4.CLK0 
clock0 => ram_block14a5.CLK0 
clock0 => ram_block14a6.CLK0 
clock0 => ram_block14a7.CLK0 
clock1 => ram_block14a0.CLK1 
clock1 => ram_block14a1.CLK1 
clock1 => ram_block14a2.CLK1 
clock1 => ram_block14a3.CLK1 
clock1 => ram_block14a4.CLK1 
clock1 => ram_block14a5.CLK1 
clock1 => ram_block14a6.CLK1 
clock1 => ram_block14a7.CLK1 
clocken1 => ram_block14a0.ENA1 
clocken1 => ram_block14a1.ENA1 
clocken1 => ram_block14a2.ENA1 
clocken1 => ram_block14a3.ENA1 
clocken1 => ram_block14a4.ENA1 
clocken1 => ram_block14a5.ENA1 
clocken1 => ram_block14a6.ENA1 
clocken1 => ram_block14a7.ENA1 
data_a[0] => ram_block14a0.PORTADATAIN 
data_a[1] => ram_block14a1.PORTADATAIN 
data_a[2] => ram_block14a2.PORTADATAIN 
data_a[3] => ram_block14a3.PORTADATAIN 
data_a[4] => ram_block14a4.PORTADATAIN 
data_a[5] => ram_block14a5.PORTADATAIN 
data_a[6] => ram_block14a6.PORTADATAIN 
data_a[7] => ram_block14a7.PORTADATAIN 
wren_a => ram_block14a0.PORTAWE 
wren_a => ram_block14a0.ENA0 
wren_a => ram_block14a1.PORTAWE 
wren_a => ram_block14a1.ENA0 
wren_a => ram_block14a2.PORTAWE 
wren_a => ram_block14a2.ENA0 
wren_a => ram_block14a3.PORTAWE 
wren_a => ram_block14a3.ENA0 
wren_a => ram_block14a4.PORTAWE 
wren_a => ram_block14a4.ENA0 
wren_a => ram_block14a5.PORTAWE 
wren_a => ram_block14a5.ENA0 
wren_a => ram_block14a6.PORTAWE 
wren_a => ram_block14a6.ENA0 
wren_a => ram_block14a7.PORTAWE 
wren_a => ram_block14a7.ENA0 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|alt_synch_pipe_b7d:rs_dgwp 
clock => dffpipe_a09:dffpipe15.clock 
d[0] => dffpipe_a09:dffpipe15.d[0] 
d[1] => dffpipe_a09:dffpipe15.d[1] 
d[2] => dffpipe_a09:dffpipe15.d[2] 
d[3] => dffpipe_a09:dffpipe15.d[3] 
d[4] => dffpipe_a09:dffpipe15.d[4] 
d[5] => dffpipe_a09:dffpipe15.d[5] 
d[6] => dffpipe_a09:dffpipe15.d[6] 
d[7] => dffpipe_a09:dffpipe15.d[7] 
d[8] => dffpipe_a09:dffpipe15.d[8] 
d[9] => dffpipe_a09:dffpipe15.d[9] 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|alt_synch_pipe_b7d:rs_dgwp|dffpipe_a09:dffpipe15 
clock => dffe16a[9].CLK 
clock => dffe16a[8].CLK 
clock => dffe16a[7].CLK 
clock => dffe16a[6].CLK 
clock => dffe16a[5].CLK 
clock => dffe16a[4].CLK 
clock => dffe16a[3].CLK 
clock => dffe16a[2].CLK 
clock => dffe16a[1].CLK 
clock => dffe16a[0].CLK 
clock => dffe17a[9].CLK 
clock => dffe17a[8].CLK 
clock => dffe17a[7].CLK 
clock => dffe17a[6].CLK 
clock => dffe17a[5].CLK 
clock => dffe17a[4].CLK 
clock => dffe17a[3].CLK 
clock => dffe17a[2].CLK 
clock => dffe17a[1].CLK 
clock => dffe17a[0].CLK 
d[0] => dffe16a[0].IN0 
d[1] => dffe16a[1].IN0 
d[2] => dffe16a[2].IN0 
d[3] => dffe16a[3].IN0 
d[4] => dffe16a[4].IN0 
d[5] => dffe16a[5].IN0 
d[6] => dffe16a[6].IN0 
d[7] => dffe16a[7].IN0 
d[8] => dffe16a[8].IN0 
d[9] => dffe16a[9].IN0 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|alt_synch_pipe_c7d:ws_dgrp 
clock => dffpipe_b09:dffpipe18.clock 
d[0] => dffpipe_b09:dffpipe18.d[0] 
d[1] => dffpipe_b09:dffpipe18.d[1] 
d[2] => dffpipe_b09:dffpipe18.d[2] 
d[3] => dffpipe_b09:dffpipe18.d[3] 
d[4] => dffpipe_b09:dffpipe18.d[4] 
d[5] => dffpipe_b09:dffpipe18.d[5] 
d[6] => dffpipe_b09:dffpipe18.d[6] 
d[7] => dffpipe_b09:dffpipe18.d[7] 
d[8] => dffpipe_b09:dffpipe18.d[8] 
d[9] => dffpipe_b09:dffpipe18.d[9] 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|alt_synch_pipe_c7d:ws_dgrp|dffpipe_b09:dffpipe18 
clock => dffe19a[9].CLK 
clock => dffe19a[8].CLK 
clock => dffe19a[7].CLK 
clock => dffe19a[6].CLK 
clock => dffe19a[5].CLK 
clock => dffe19a[4].CLK 
clock => dffe19a[3].CLK 
clock => dffe19a[2].CLK 
clock => dffe19a[1].CLK 
clock => dffe19a[0].CLK 
clock => dffe20a[9].CLK 
clock => dffe20a[8].CLK 
clock => dffe20a[7].CLK 
clock => dffe20a[6].CLK 
clock => dffe20a[5].CLK 
clock => dffe20a[4].CLK 
clock => dffe20a[3].CLK 
clock => dffe20a[2].CLK 
clock => dffe20a[1].CLK 
clock => dffe20a[0].CLK 
d[0] => dffe19a[0].IN0 
d[1] => dffe19a[1].IN0 
d[2] => dffe19a[2].IN0 
d[3] => dffe19a[3].IN0 
d[4] => dffe19a[4].IN0 
d[5] => dffe19a[5].IN0 
d[6] => dffe19a[6].IN0 
d[7] => dffe19a[7].IN0 
d[8] => dffe19a[8].IN0 
d[9] => dffe19a[9].IN0 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|cmpr_n76:rdempty_eq_comp 
dataa[0] => data_wire[2].IN0 
dataa[1] => data_wire[2].IN0 
dataa[2] => data_wire[3].IN0 
dataa[3] => data_wire[3].IN0 
dataa[4] => data_wire[4].IN0 
dataa[5] => data_wire[4].IN0 
dataa[6] => data_wire[5].IN0 
dataa[7] => data_wire[5].IN0 
dataa[8] => data_wire[6].IN0 
dataa[9] => data_wire[6].IN0 
datab[0] => data_wire[2].IN1 
datab[1] => data_wire[2].IN1 
datab[2] => data_wire[3].IN1 
datab[3] => data_wire[3].IN1 
datab[4] => data_wire[4].IN1 
datab[5] => data_wire[4].IN1 
datab[6] => data_wire[5].IN1 
datab[7] => data_wire[5].IN1 
datab[8] => data_wire[6].IN1 
datab[9] => data_wire[6].IN1 
 
 
|SD_Card|sd_spi_secrd:uut_sd_spi_secrd|rw_fifo:rd_fifo|dcfifo:dcfifo_component|dcfifo_jse1:auto_generated|cmpr_n76:wrfull_eq_comp 
dataa[0] => data_wire[2].IN0 
dataa[1] => data_wire[2].IN0 
dataa[2] => data_wire[3].IN0 
dataa[3] => data_wire[3].IN0 
dataa[4] => data_wire[4].IN0 
dataa[5] => data_wire[4].IN0 
dataa[6] => data_wire[5].IN0 
dataa[7] => data_wire[5].IN0 
dataa[8] => data_wire[6].IN0 
dataa[9] => data_wire[6].IN0 
datab[0] => data_wire[2].IN1 
datab[1] => data_wire[2].IN1 
datab[2] => data_wire[3].IN1 
datab[3] => data_wire[3].IN1 
datab[4] => data_wire[4].IN1 
datab[5] => data_wire[4].IN1 
datab[6] => data_wire[5].IN1 
datab[7] => data_wire[5].IN1 
datab[8] => data_wire[6].IN1 
datab[9] => data_wire[6].IN1