www.pudn.com > MyFCS1.zip > dffpipe_93c.tdf, change:2014-05-04,size:1313b


--dffpipe CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DELAY=0 WIDTH=32 d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF 
--VERSION_BEGIN 11.0 cbx_mgl 2011:04:27:21:08:59:SJ cbx_stratixii 2011:04:27:21:07:09:SJ cbx_util_mgl 2011:04:27:21:07:09:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2011 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
 
--synthesis_resources =  
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF"; 
 
SUBDESIGN dffpipe_93c 
(  
	d[31..0]	:	input; 
	q[31..0]	:	output; 
)  
 
BEGIN  
	q[] = d[]; 
END; 
--VALID FILE