www.pudn.com > MyFCS1.zip > CPU_MyFCS3.ptf, change:2014-06-10,size:102095b


SYSTEM CPU_MyFCS3 
{ 
   System_Wizard_Version = "11.00"; 
   System_Wizard_Build = "157"; 
   Builder_Application = "sopc_builder_ca"; 
   WIZARD_SCRIPT_ARGUMENTS  
   { 
      hdl_language = "verilog"; 
      device_family = "CYCLONEII"; 
      device_family_id = "CYCLONEII"; 
      generate_sdk = "0"; 
      do_build_sim = "0"; 
      hardcopy_compatible = "0"; 
      CLOCKS  
      { 
         CLOCK clk_0 
         { 
            frequency = "50000000"; 
            source = "External"; 
            Is_Clock_Source = "0"; 
            display_name = "clk_0"; 
            pipeline = "0"; 
            clock_module_connection_point_for_c2h = "clk_0.clk"; 
         } 
      } 
      clock_freq = "50000000"; 
      clock_freq = "50000000"; 
      board_class = ""; 
      view_master_columns = "1"; 
      view_master_priorities = "0"; 
      generate_hdl = ""; 
      bustype_column_width = "0"; 
      clock_column_width = "80"; 
      name_column_width = "75"; 
      desc_column_width = "75"; 
      base_column_width = "75"; 
      end_column_width = "75"; 
      BOARD_INFO  
      { 
         altera_avalon_epcs_flash_controller  
         { 
            reference_designators = ""; 
         } 
      } 
      do_log_history = "0"; 
   } 
   MODULE EP2C8 
   { 
      MASTER instruction_master 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "0"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "0"; 
            } 
            PORT i_address 
            { 
               type = "address"; 
               width = "27"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT i_read 
            { 
               type = "read"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT i_readdata 
            { 
               type = "readdata"; 
               width = "32"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT i_readdatavalid 
            { 
               type = "readdatavalid"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT i_waitrequest 
            { 
               type = "waitrequest"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT jtag_debug_module_resetrequest 
            { 
               type = "resetrequest"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "0"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Bus_Type = "avalon"; 
            Is_Asynchronous = "0"; 
            DBS_Big_Endian = "0"; 
            Adapts_To = ""; 
            Do_Stream_Reads = "0"; 
            Do_Stream_Writes = "0"; 
            Max_Address_Width = "32"; 
            Data_Width = "32"; 
            Address_Width = "27"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = ""; 
            Linewrap_Bursts = ""; 
            Burst_On_Burst_Boundaries_Only = ""; 
            Always_Burst_Max_Burst = ""; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            Is_Instruction_Master = "1"; 
            Is_Readable = "1"; 
            Is_Writeable = "0"; 
            Address_Group = "0"; 
            Has_IRQ = "0"; 
            Irq_Scheme = "individual_requests"; 
            Interrupt_Range = "0-0"; 
         } 
         MEMORY_MAP  
         { 
            Entry EP2C8/jtag_debug_module 
            { 
               address = "0x00001000"; 
               span = "0x00000800"; 
               is_bridge = "0"; 
            } 
            Entry sdram/s1 
            { 
               address = "0x04000000"; 
               span = "0x02000000"; 
               is_bridge = "0"; 
            } 
            Entry epcs/epcs_control_port 
            { 
               address = "0x00000000"; 
               span = "0x00000800"; 
               is_bridge = "0"; 
            } 
         } 
      } 
      MASTER custom_instruction_master 
      { 
         SYSTEM_BUILDER_INFO  
         { 
            Bus_Type = "nios_custom_instruction"; 
            Data_Width = "32"; 
            Address_Width = "8"; 
            Is_Custom_Instruction = "1"; 
            Is_Enabled = "0"; 
            Max_Address_Width = "8"; 
            Base_Address = "N/A"; 
            Is_Visible = "0"; 
         } 
         PORT_WIRING  
         { 
            PORT dataa 
            { 
               type = "dataa"; 
               width = "32"; 
               direction = "output"; 
            } 
            PORT datab 
            { 
               type = "datab"; 
               width = "32"; 
               direction = "output"; 
            } 
            PORT result 
            { 
               type = "result"; 
               width = "32"; 
               direction = "input"; 
            } 
            PORT clk_en 
            { 
               type = "clk_en"; 
               width = "1"; 
               direction = "output"; 
            } 
            PORT reset 
            { 
               type = "reset"; 
               width = "1"; 
               direction = "output"; 
            } 
            PORT start 
            { 
               type = "start"; 
               width = "1"; 
               direction = "output"; 
            } 
            PORT done 
            { 
               type = "done"; 
               width = "1"; 
               direction = "input"; 
            } 
            PORT n 
            { 
               type = "n"; 
               width = "8"; 
               direction = "output"; 
            } 
            PORT a 
            { 
               type = "a"; 
               width = "5"; 
               direction = "output"; 
            } 
            PORT b 
            { 
               type = "b"; 
               width = "5"; 
               direction = "output"; 
            } 
            PORT c 
            { 
               type = "c"; 
               width = "5"; 
               direction = "output"; 
            } 
            PORT readra 
            { 
               type = "readra"; 
               width = "1"; 
               direction = "output"; 
            } 
            PORT readrb 
            { 
               type = "readrb"; 
               width = "1"; 
               direction = "output"; 
            } 
            PORT writerc 
            { 
               type = "writerc"; 
               width = "1"; 
               direction = "output"; 
            } 
         } 
      } 
      SLAVE jtag_debug_module 
      { 
         SYSTEM_BUILDER_INFO  
         { 
            Bus_Type = "avalon"; 
            Write_Wait_States = "0cycles"; 
            Read_Wait_States = "1cycles"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "0"; 
            Address_Alignment = "dynamic"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "0"; 
            Address_Span = "2048"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "1"; 
            Maximum_Pending_Read_Transactions = "0"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "0"; 
            Data_Width = "32"; 
            Address_Width = "9"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            Accepts_External_Connections = "1"; 
            Requires_Internal_Connections = ""; 
            MASTERED_BY EP2C8/instruction_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00001000"; 
            } 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00001000"; 
            } 
            Base_Address = "0x00001000"; 
            Is_Readable = "1"; 
            Is_Writeable = "1"; 
            Uses_Tri_State_Data_Bus = "0"; 
            Has_IRQ = "0"; 
            JTAG_Hub_Base_Id = "1118278"; 
            JTAG_Hub_Instance_Id = "0"; 
            Address_Group = "0"; 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "NC"; 
            } 
         } 
         PORT_WIRING  
         { 
            PORT jtag_debug_module_address 
            { 
               type = "address"; 
               width = "9"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT jtag_debug_module_begintransfer 
            { 
               type = "begintransfer"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT jtag_debug_module_byteenable 
            { 
               type = "byteenable"; 
               width = "4"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT jtag_debug_module_debugaccess 
            { 
               type = "debugaccess"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT jtag_debug_module_readdata 
            { 
               type = "readdata"; 
               width = "32"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT jtag_debug_module_select 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT jtag_debug_module_write 
            { 
               type = "write"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT jtag_debug_module_writedata 
            { 
               type = "writedata"; 
               width = "32"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT clk 
            { 
               Is_Enabled = "1"; 
               direction = "input"; 
               type = "clk"; 
               width = "1"; 
            } 
            PORT jtag_debug_module_resetrequest 
            { 
               Is_Enabled = "1"; 
               direction = "output"; 
               type = "resetrequest"; 
               width = "1"; 
            } 
            PORT reset_n 
            { 
               Is_Enabled = "1"; 
               direction = "input"; 
               type = "reset_n"; 
               width = "1"; 
            } 
         } 
      } 
      MASTER data_master 
      { 
         SYSTEM_BUILDER_INFO  
         { 
            Has_IRQ = "1"; 
            Irq_Scheme = "individual_requests"; 
            Bus_Type = "avalon"; 
            Is_Asynchronous = "0"; 
            DBS_Big_Endian = "0"; 
            Adapts_To = ""; 
            Do_Stream_Reads = "0"; 
            Do_Stream_Writes = "0"; 
            Max_Address_Width = "32"; 
            Data_Width = "32"; 
            Address_Width = "27"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "1"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = ""; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            Is_Data_Master = "1"; 
            Address_Group = "0"; 
            Is_Readable = "1"; 
            Is_Writeable = "1"; 
            Interrupt_Range = "0-31"; 
         } 
         PORT_WIRING  
         { 
            PORT d_irq 
            { 
               type = "irq"; 
               width = "32"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT d_address 
            { 
               type = "address"; 
               width = "27"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT d_byteenable 
            { 
               type = "byteenable"; 
               width = "4"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT d_read 
            { 
               type = "read"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT d_readdata 
            { 
               type = "readdata"; 
               width = "32"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT d_readdatavalid 
            { 
               type = "readdatavalid"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "0"; 
            } 
            PORT d_waitrequest 
            { 
               type = "waitrequest"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT d_write 
            { 
               type = "write"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT d_writedata 
            { 
               type = "writedata"; 
               width = "32"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT jtag_debug_module_debugaccess_to_roms 
            { 
               type = "debugaccess"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
         } 
         MEMORY_MAP  
         { 
            Entry EP2C8/jtag_debug_module 
            { 
               address = "0x00001000"; 
               span = "0x00000800"; 
               is_bridge = "0"; 
            } 
            Entry sdram/s1 
            { 
               address = "0x04000000"; 
               span = "0x02000000"; 
               is_bridge = "0"; 
            } 
            Entry uart/s1 
            { 
               address = "0x00001800"; 
               span = "0x00000020"; 
               is_bridge = "0"; 
            } 
            Entry epcs/epcs_control_port 
            { 
               address = "0x00000000"; 
               span = "0x00000800"; 
               is_bridge = "0"; 
            } 
            Entry TIM2/s1 
            { 
               address = "0x00001820"; 
               span = "0x00000020"; 
               is_bridge = "0"; 
            } 
            Entry watchdog/s1 
            { 
               address = "0x00001840"; 
               span = "0x00000020"; 
               is_bridge = "0"; 
            } 
            Entry SCL/s1 
            { 
               address = "0x00001880"; 
               span = "0x00000010"; 
               is_bridge = "0"; 
            } 
            Entry SDA/s1 
            { 
               address = "0x00001890"; 
               span = "0x00000010"; 
               is_bridge = "0"; 
            } 
            Entry LED/s1 
            { 
               address = "0x000018a0"; 
               span = "0x00000010"; 
               is_bridge = "0"; 
            } 
            Entry TIM1/s1 
            { 
               address = "0x00001860"; 
               span = "0x00000020"; 
               is_bridge = "0"; 
            } 
         } 
      } 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         cache_has_dcache = "0"; 
         cache_dcache_size = "0"; 
         cache_dcache_line_size = "0"; 
         cache_dcache_bursts = "0"; 
         cache_dcache_ram_block_type = "AUTO"; 
         num_tightly_coupled_data_masters = "0"; 
         gui_num_tightly_coupled_data_masters = "0"; 
         gui_include_tightly_coupled_data_masters = "0"; 
         gui_omit_avalon_data_master = "0"; 
         cache_has_icache = "1"; 
         cache_icache_size = "4096"; 
         cache_icache_line_size = "32"; 
         cache_icache_ram_block_type = "AUTO"; 
         cache_icache_bursts = "0"; 
         num_tightly_coupled_instruction_masters = "0"; 
         gui_num_tightly_coupled_instruction_masters = "0"; 
         gui_include_tightly_coupled_instruction_masters = "0"; 
         debug_level = "2"; 
         include_oci = "1"; 
         oci_num_xbrk = "0"; 
         oci_num_dbrk = "0"; 
         oci_dbrk_trace = "0"; 
         oci_dbrk_pairs = "0"; 
         oci_onchip_trace = "0"; 
         oci_offchip_trace = "0"; 
         oci_data_trace = "0"; 
         include_third_party_debug_port = "0"; 
         oci_trace_addr_width = "7"; 
         oci_debugreq_signals = "0"; 
         oci_trigger_arming = "1"; 
         oci_embedded_pll = "0"; 
         oci_assign_jtag_instance_id = "0"; 
         oci_jtag_instance_id = "0"; 
         oci_num_pm = "0"; 
         oci_pm_width = "32"; 
         performance_counters_present = "0"; 
         performance_counters_width = "32"; 
         always_encrypt = "1"; 
         debug_simgen = "0"; 
         activate_model_checker = "0"; 
         activate_test_end_checker = "0"; 
         activate_trace = "1"; 
         activate_monitors = "1"; 
         clear_x_bits_ld_non_bypass = "1"; 
         bit_31_bypass_dcache = "1"; 
         hdl_sim_caches_cleared = "1"; 
         hbreak_test = "0"; 
         allow_full_address_range = "0"; 
         extra_exc_info = "0"; 
         branch_prediction_type = "Dynamic"; 
         bht_ptr_sz = "8"; 
         bht_index_pc_only = "0"; 
         gui_branch_prediction_type = "Automatic"; 
         full_waveform_signals = "0"; 
         export_pcb = "0"; 
         big_endian = "0"; 
         avalon_debug_port_present = "0"; 
         illegal_instructions_trap = "0"; 
         illegal_memory_access_detection = "0"; 
         illegal_mem_exc = "0"; 
         slave_access_error_exc = "0"; 
         division_error_exc = "0"; 
         eic_present = "0"; 
         num_shadow_reg_sets = "0"; 
         gui_mmu_present = "0"; 
         mmu_present = "0"; 
         process_id_num_bits = "8"; 
         tlb_ptr_sz = "7"; 
         tlb_num_ways = "16"; 
         udtlb_num_entries = "6"; 
         uitlb_num_entries = "4"; 
         fast_tlb_miss_exc_slave = ""; 
         fast_tlb_miss_exc_offset = "0x00000000"; 
         mpu_present = "0"; 
         mpu_num_data_regions = "8"; 
         mpu_num_inst_regions = "8"; 
         mpu_min_data_region_size_log2 = "12"; 
         mpu_min_inst_region_size_log2 = "12"; 
         mpu_use_limit = "0"; 
         hardware_divide_present = "0"; 
         gui_hardware_divide_setting = "0"; 
         hardware_multiply_present = "1"; 
         hardware_multiply_impl = "embedded_mul"; 
         shift_rot_impl = "fast_le_shift"; 
         gui_hardware_multiply_setting = "embedded_mul_fast_le_shift"; 
         reset_slave = "epcs/epcs_control_port"; 
         break_slave = "EP2C8/jtag_debug_module"; 
         exc_slave = "sdram/s1"; 
         reset_offset = "0x00000000"; 
         break_offset = "0x00000020"; 
         exc_offset = "0x00000020"; 
         cpu_reset = "0"; 
         CPU_Implementation = "fast"; 
         cpu_selection = "f"; 
         device_family_id = "CYCLONEII"; 
         address_stall_present = "1"; 
         dsp_block_supports_shift = "0"; 
         mrams_present = "0"; 
         cpuid_value = "0"; 
         dont_overwrite_cpuid = "1"; 
         allow_legacy_sdk = "1"; 
         legacy_sdk_support = "1"; 
         inst_addr_width = "27"; 
         data_addr_width = "27"; 
         CPU_Architecture = "nios2"; 
         cache_icache_burst_type = "none"; 
         oci_sync_depth = "2"; 
         hardware_divide_impl = "variable_latency"; 
         hardware_multiply_omits_msw = "1"; 
         break_slave_override = ""; 
         break_offset_override = "0x20"; 
         altera_show_unreleased_features = "0"; 
         altera_show_unpublished_features = "0"; 
         altera_internal_test = "0"; 
         alt_log_port_base = ""; 
         alt_log_port_type = ""; 
         cpuid_sz = "1"; 
         gui_illegal_instructions_trap = "0"; 
         advanced_exc = "0"; 
         gui_illegal_memory_access_detection = "0"; 
         cache_omit_dcache = "0"; 
         cache_omit_icache = "0"; 
         omit_instruction_master = "0"; 
         omit_data_master = "0"; 
         ras_ptr_sz = "4"; 
         jtb_ptr_sz = "5"; 
         ibuf_ptr_sz = "4"; 
         always_bypass_dcache = "0"; 
         iss_trace_on = "0"; 
         iss_trace_warning = "1"; 
         iss_trace_info = "1"; 
         iss_trace_disassembly = "0"; 
         iss_trace_registers = "0"; 
         iss_trace_instr_count = "0"; 
         iss_software_debug = "0"; 
         iss_software_debug_port = "9996"; 
         iss_memory_dump_start = ""; 
         iss_memory_dump_end = ""; 
         Boot_Copier = "boot_loader_cfi.srec"; 
         Boot_Copier_EPCS = "boot_loader_epcs.srec"; 
         Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec"; 
         Boot_Copier_BE = "boot_loader_cfi_be.srec"; 
         Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec"; 
         Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec"; 
         CONSTANTS  
         { 
            CONSTANT __nios_catch_irqs__ 
            { 
               value = "1"; 
               comment = "Include panic handler for all irqs (needs uart)"; 
            } 
            CONSTANT __nios_use_constructors__ 
            { 
               value = "1"; 
               comment = "Call c++ static constructors"; 
            } 
            CONSTANT __nios_use_small_printf__ 
            { 
               value = "1"; 
               comment = "Smaller non-ANSI printf, with no floating point"; 
            } 
            CONSTANT nasys_has_icache 
            { 
               value = "1"; 
               comment = "True if instruction cache present"; 
            } 
            CONSTANT nasys_icache_size 
            { 
               value = "4096"; 
               comment = "Size in bytes of instruction cache"; 
            } 
            CONSTANT nasys_icache_line_size 
            { 
               value = "32"; 
               comment = "Size in bytes of each icache line"; 
            } 
            CONSTANT nasys_icache_line_size_log2 
            { 
               value = "5"; 
               comment = "Log2 size in bytes of each icache line"; 
            } 
            CONSTANT nasys_has_dcache 
            { 
               value = "0"; 
               comment = "True if instruction cache present"; 
            } 
            CONSTANT nasys_dcache_size 
            { 
               value = "0"; 
               comment = "Size in bytes of data cache"; 
            } 
            CONSTANT nasys_dcache_line_size 
            { 
               value = "0"; 
               comment = "Size in bytes of each dcache line"; 
            } 
            CONSTANT nasys_dcache_line_size_log2 
            { 
               value = "-Infinity"; 
               comment = "Log2 size in bytes of each dcache line"; 
            } 
         } 
         license_status = "encrypted"; 
         mainmem_slave = "epcs/epcs_control_port"; 
         datamem_slave = "epcs/epcs_control_port"; 
         maincomm_slave = "uart/s1"; 
         germs_monitor_id = ""; 
      } 
      class = "altera_nios2"; 
      class_version = "7.08110"; 
      SYSTEM_BUILDER_INFO  
      { 
         Is_Enabled = "1"; 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
         Parameters_Signature = ""; 
         Is_CPU = "1"; 
         Instantiate_In_System_Module = "1"; 
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,STRATIXV,CYCLONE,CYCLONEII,CYCLONEIII,CYCLONEIVE,HARDCOPYIII,ARRIAII,ARRIAIIGZ,TARPON,HARDCOPYIV,STINGRAY"; 
         Default_Module_Name = "cpu"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         View  
         { 
            Settings_Summary = "Nios II/f 
            <br>  4-Kbyte Instruction Cache 
             
            <br>  JTAG Debug Module 
            "; 
            MESSAGES  
            { 
            } 
         } 
      } 
      iss_model_name = "altera_nios2"; 
      HDL_INFO  
      { 
         PLI_Files = ""; 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/EP2C8_test_bench.v, __PROJECT_DIRECTORY__/EP2C8_mult_cell.v, __PROJECT_DIRECTORY__/EP2C8_oci_test_bench.v, __PROJECT_DIRECTORY__/EP2C8_jtag_debug_module_tck.v, __PROJECT_DIRECTORY__/EP2C8_jtag_debug_module_sysclk.v, __PROJECT_DIRECTORY__/EP2C8_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/EP2C8.v"; 
         Synthesis_Only_Files = ""; 
      } 
      MASTER tightly_coupled_instruction_master_0 
      { 
         PORT_WIRING  
         { 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Register_Incoming_Signals = "0"; 
            Bus_Type = "avalon"; 
            Data_Width = "32"; 
            Max_Address_Width = "31"; 
            Address_Width = "8"; 
            Is_Instruction_Master = "1"; 
            Has_IRQ = "0"; 
            Is_Enabled = "0"; 
            Is_Big_Endian = "0"; 
            Connection_Limit = "1"; 
            Is_Channel = "1"; 
         } 
      } 
      MASTER tightly_coupled_instruction_master_1 
      { 
         PORT_WIRING  
         { 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Register_Incoming_Signals = "0"; 
            Bus_Type = "avalon"; 
            Data_Width = "32"; 
            Max_Address_Width = "31"; 
            Address_Width = "8"; 
            Address_Group = "0"; 
            Is_Instruction_Master = "1"; 
            Is_Readable = "1"; 
            Is_Writeable = "0"; 
            Has_IRQ = "0"; 
            Is_Enabled = "0"; 
            Is_Big_Endian = "0"; 
            Connection_Limit = "1"; 
            Is_Channel = "1"; 
         } 
      } 
      MASTER tightly_coupled_instruction_master_2 
      { 
         PORT_WIRING  
         { 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Register_Incoming_Signals = "0"; 
            Bus_Type = "avalon"; 
            Data_Width = "32"; 
            Max_Address_Width = "31"; 
            Address_Width = "8"; 
            Address_Group = "0"; 
            Is_Instruction_Master = "1"; 
            Is_Readable = "1"; 
            Is_Writeable = "0"; 
            Has_IRQ = "0"; 
            Is_Enabled = "0"; 
            Is_Big_Endian = "0"; 
            Connection_Limit = "1"; 
            Is_Channel = "1"; 
         } 
      } 
      MASTER tightly_coupled_instruction_master_3 
      { 
         PORT_WIRING  
         { 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Register_Incoming_Signals = "0"; 
            Bus_Type = "avalon"; 
            Data_Width = "32"; 
            Max_Address_Width = "31"; 
            Address_Width = "8"; 
            Address_Group = "0"; 
            Is_Instruction_Master = "1"; 
            Is_Readable = "1"; 
            Is_Writeable = "0"; 
            Has_IRQ = "0"; 
            Is_Enabled = "0"; 
            Is_Big_Endian = "0"; 
            Connection_Limit = "1"; 
            Is_Channel = "1"; 
         } 
      } 
      MASTER data_master2 
      { 
         PORT_WIRING  
         { 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Register_Incoming_Signals = "1"; 
            Bus_Type = "avalon"; 
            Data_Width = "32"; 
            Max_Address_Width = "31"; 
            Address_Width = "8"; 
            Address_Group = "0"; 
            Is_Data_Master = "1"; 
            Is_Readable = "1"; 
            Is_Writeable = "1"; 
            Has_IRQ = "0"; 
            Is_Enabled = "0"; 
            Is_Big_Endian = "0"; 
         } 
      } 
      MASTER tightly_coupled_data_master_0 
      { 
         PORT_WIRING  
         { 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Register_Incoming_Signals = "0"; 
            Bus_Type = "avalon"; 
            Data_Width = "32"; 
            Max_Address_Width = "31"; 
            Address_Width = "8"; 
            Address_Group = "0"; 
            Is_Data_Master = "1"; 
            Is_Readable = "1"; 
            Is_Writeable = "1"; 
            Has_IRQ = "0"; 
            Is_Enabled = "0"; 
            Is_Big_Endian = "0"; 
            Connection_Limit = "1"; 
            Is_Channel = "1"; 
         } 
      } 
      MASTER tightly_coupled_data_master_1 
      { 
         PORT_WIRING  
         { 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Register_Incoming_Signals = "0"; 
            Bus_Type = "avalon"; 
            Data_Width = "32"; 
            Max_Address_Width = "31"; 
            Address_Width = "8"; 
            Address_Group = "0"; 
            Is_Data_Master = "1"; 
            Is_Readable = "1"; 
            Is_Writeable = "1"; 
            Has_IRQ = "0"; 
            Is_Enabled = "0"; 
            Is_Big_Endian = "0"; 
            Connection_Limit = "1"; 
            Is_Channel = "1"; 
         } 
      } 
      MASTER tightly_coupled_data_master_2 
      { 
         PORT_WIRING  
         { 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Register_Incoming_Signals = "0"; 
            Bus_Type = "avalon"; 
            Data_Width = "32"; 
            Max_Address_Width = "31"; 
            Address_Width = "8"; 
            Address_Group = "0"; 
            Is_Data_Master = "1"; 
            Is_Readable = "1"; 
            Is_Writeable = "1"; 
            Has_IRQ = "0"; 
            Is_Enabled = "0"; 
            Is_Big_Endian = "0"; 
            Connection_Limit = "1"; 
            Is_Channel = "1"; 
         } 
      } 
      MASTER tightly_coupled_data_master_3 
      { 
         PORT_WIRING  
         { 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Register_Incoming_Signals = "0"; 
            Bus_Type = "avalon"; 
            Data_Width = "32"; 
            Max_Address_Width = "31"; 
            Address_Width = "8"; 
            Address_Group = "0"; 
            Is_Data_Master = "1"; 
            Is_Readable = "1"; 
            Is_Writeable = "1"; 
            Has_IRQ = "0"; 
            Is_Enabled = "0"; 
            Is_Big_Endian = "0"; 
            Connection_Limit = "1"; 
            Is_Channel = "1"; 
         } 
      } 
      PORT_WIRING  
      { 
         PORT jtag_debug_trigout 
         { 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT jtag_debug_offchip_trace_clk 
         { 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT jtag_debug_offchip_trace_data 
         { 
            width = "18"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT clkx2 
         { 
            width = "1"; 
            direction = "input"; 
            Is_Enabled = "0"; 
            visible = "0"; 
         } 
      } 
      SIMULATION  
      { 
         DISPLAY  
         { 
            SIGNAL aaa 
            { 
               format = "Logic"; 
               name = "i_readdata"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aab 
            { 
               format = "Logic"; 
               name = "i_readdatavalid"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aac 
            { 
               format = "Logic"; 
               name = "i_waitrequest"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aad 
            { 
               format = "Logic"; 
               name = "i_address"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aae 
            { 
               format = "Logic"; 
               name = "i_read"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aaf 
            { 
               format = "Logic"; 
               name = "clk"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aag 
            { 
               format = "Logic"; 
               name = "reset_n"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aah 
            { 
               format = "Logic"; 
               name = "d_readdata"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aai 
            { 
               format = "Logic"; 
               name = "d_waitrequest"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aaj 
            { 
               format = "Logic"; 
               name = "d_address"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aak 
            { 
               format = "Logic"; 
               name = "d_byteenable"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aal 
            { 
               format = "Logic"; 
               name = "d_read"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aam 
            { 
               format = "Logic"; 
               name = "d_write"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aan 
            { 
               format = "Logic"; 
               name = "d_writedata"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aao 
            { 
               format = "Logic"; 
               name = "d_irq"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aap 
            { 
               format = "Divider"; 
               name = "base pipeline"; 
               radix = ""; 
            } 
            SIGNAL aaq 
            { 
               format = "Logic"; 
               name = "clk"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aar 
            { 
               format = "Logic"; 
               name = "reset_n"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aas 
            { 
               format = "Logic"; 
               name = "D_stall"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aat 
            { 
               format = "Logic"; 
               name = "A_stall"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aau 
            { 
               format = "Logic"; 
               name = "F_pcb_nxt"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aav 
            { 
               format = "Logic"; 
               name = "F_pcb"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aaw 
            { 
               format = "Logic"; 
               name = "D_pcb"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aax 
            { 
               format = "Logic"; 
               name = "E_pcb"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aay 
            { 
               format = "Logic"; 
               name = "M_pcb"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aaz 
            { 
               format = "Logic"; 
               name = "A_pcb"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aba 
            { 
               format = "Logic"; 
               name = "W_pcb"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abb 
            { 
               format = "Logic"; 
               name = "F_vinst"; 
               radix = "ascii"; 
            } 
            SIGNAL abc 
            { 
               format = "Logic"; 
               name = "D_vinst"; 
               radix = "ascii"; 
            } 
            SIGNAL abd 
            { 
               format = "Logic"; 
               name = "E_vinst"; 
               radix = "ascii"; 
            } 
            SIGNAL abe 
            { 
               format = "Logic"; 
               name = "M_vinst"; 
               radix = "ascii"; 
            } 
            SIGNAL abf 
            { 
               format = "Logic"; 
               name = "A_vinst"; 
               radix = "ascii"; 
            } 
            SIGNAL abg 
            { 
               format = "Logic"; 
               name = "W_vinst"; 
               radix = "ascii"; 
            } 
            SIGNAL abh 
            { 
               format = "Logic"; 
               name = "F_inst_ram_hit"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abi 
            { 
               format = "Logic"; 
               name = "F_iw_valid"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abj 
            { 
               format = "Logic"; 
               name = "F_issue"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abk 
            { 
               format = "Logic"; 
               name = "F_kill"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abl 
            { 
               format = "Logic"; 
               name = "D_kill"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abm 
            { 
               format = "Logic"; 
               name = "D_refetch"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abn 
            { 
               format = "Logic"; 
               name = "D_issue"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abo 
            { 
               format = "Logic"; 
               name = "D_valid"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abp 
            { 
               format = "Logic"; 
               name = "D_rdprs_stall"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abq 
            { 
               format = "Logic"; 
               name = "D_rdprs_stall_done"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abr 
            { 
               format = "Logic"; 
               name = "E_valid"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abs 
            { 
               format = "Logic"; 
               name = "M_valid"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abt 
            { 
               format = "Logic"; 
               name = "A_valid"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abu 
            { 
               format = "Logic"; 
               name = "W_valid"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abv 
            { 
               format = "Logic"; 
               name = "W_wr_dst_reg"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abw 
            { 
               format = "Logic"; 
               name = "W_dst_regnum"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abx 
            { 
               format = "Logic"; 
               name = "W_wr_data"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aby 
            { 
               format = "Logic"; 
               name = "D_en"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL abz 
            { 
               format = "Logic"; 
               name = "E_en"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aca 
            { 
               format = "Logic"; 
               name = "M_en"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acb 
            { 
               format = "Logic"; 
               name = "A_en"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acc 
            { 
               format = "Logic"; 
               name = "F_iw"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acd 
            { 
               format = "Logic"; 
               name = "D_iw"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL ace 
            { 
               format = "Logic"; 
               name = "E_iw"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acf 
            { 
               format = "Logic"; 
               name = "M_pipe_flush"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acg 
            { 
               format = "Logic"; 
               name = "M_pipe_flush_baddr"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL ach 
            { 
               format = "Logic"; 
               name = "norm_intr_req"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aci 
            { 
               format = "Logic"; 
               name = "A_status_reg"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acj 
            { 
               format = "Logic"; 
               name = "A_status_reg_pie"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL ack 
            { 
               format = "Logic"; 
               name = "A_estatus_reg"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acl 
            { 
               format = "Logic"; 
               name = "A_estatus_reg_pie"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acm 
            { 
               format = "Logic"; 
               name = "A_bstatus_reg"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acn 
            { 
               format = "Logic"; 
               name = "A_bstatus_reg_pie"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL aco 
            { 
               format = "Logic"; 
               name = "A_ienable_reg"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acp 
            { 
               format = "Logic"; 
               name = "A_ienable_reg_irq0"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acq 
            { 
               format = "Logic"; 
               name = "A_ienable_reg_irq1"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acr 
            { 
               format = "Logic"; 
               name = "A_ienable_reg_irq2"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acs 
            { 
               format = "Logic"; 
               name = "A_ienable_reg_irq3"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL act 
            { 
               format = "Logic"; 
               name = "A_ienable_reg_irq4"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acu 
            { 
               format = "Logic"; 
               name = "A_ipending_reg"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acv 
            { 
               format = "Logic"; 
               name = "A_ipending_reg_irq0"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acw 
            { 
               format = "Logic"; 
               name = "A_ipending_reg_irq1"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acx 
            { 
               format = "Logic"; 
               name = "A_ipending_reg_irq2"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acy 
            { 
               format = "Logic"; 
               name = "A_ipending_reg_irq3"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL acz 
            { 
               format = "Logic"; 
               name = "A_ipending_reg_irq4"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL ada 
            { 
               format = "Logic"; 
               name = "A_cpuid_reg"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL adb 
            { 
               format = "Logic"; 
               name = "E_valid_prior_to_hbreak"; 
               radix = "hexadecimal"; 
            } 
         } 
      } 
   } 
   MODULE sdram 
   { 
      SLAVE s1 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT az_addr 
            { 
               type = "address"; 
               width = "24"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT az_be_n 
            { 
               type = "byteenable_n"; 
               width = "2"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT az_cs 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT az_data 
            { 
               type = "writedata"; 
               width = "16"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT az_rd_n 
            { 
               type = "read_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT az_wr_n 
            { 
               type = "write_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT za_data 
            { 
               type = "readdata"; 
               width = "16"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT za_valid 
            { 
               type = "readdatavalid"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT za_waitrequest 
            { 
               type = "waitrequest"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT zs_addr 
            { 
               direction = "output"; 
               width = "13"; 
               Is_Enabled = "1"; 
            } 
            PORT zs_ba 
            { 
               direction = "output"; 
               width = "2"; 
               Is_Enabled = "1"; 
            } 
            PORT zs_cas_n 
            { 
               direction = "output"; 
               width = "1"; 
               Is_Enabled = "1"; 
            } 
            PORT zs_cke 
            { 
               direction = "output"; 
               width = "1"; 
               Is_Enabled = "1"; 
            } 
            PORT zs_cs_n 
            { 
               direction = "output"; 
               width = "1"; 
               Is_Enabled = "1"; 
            } 
            PORT zs_dq 
            { 
               direction = "inout"; 
               width = "16"; 
               Is_Enabled = "1"; 
            } 
            PORT zs_dqm 
            { 
               direction = "output"; 
               width = "2"; 
               Is_Enabled = "1"; 
            } 
            PORT zs_ras_n 
            { 
               direction = "output"; 
               width = "1"; 
               Is_Enabled = "1"; 
            } 
            PORT zs_we_n 
            { 
               direction = "output"; 
               width = "1"; 
               Is_Enabled = "1"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Bus_Type = "avalon"; 
            Read_Wait_States = "peripheral_controlled"; 
            Write_Wait_States = "peripheral_controlled"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "0"; 
            Address_Alignment = "dynamic"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "0"; 
            Address_Span = "33554432"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "1"; 
            Maximum_Pending_Read_Transactions = "7"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "0"; 
            Data_Width = "16"; 
            Address_Width = "24"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            MASTERED_BY EP2C8/instruction_master 
            { 
               priority = "1"; 
               Offset_Address = "0x04000000"; 
            } 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x04000000"; 
            } 
            Base_Address = "0x04000000"; 
            Has_IRQ = "0"; 
            Simulation_Num_Lanes = "1"; 
            Address_Group = "0"; 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "NC"; 
            } 
         } 
      } 
      PORT_WIRING  
      { 
         PORT zs_addr 
         { 
            type = "export"; 
            width = "13"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT zs_ba 
         { 
            type = "export"; 
            width = "2"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT zs_cas_n 
         { 
            type = "export"; 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT zs_cke 
         { 
            type = "export"; 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT zs_cs_n 
         { 
            type = "export"; 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT zs_dq 
         { 
            type = "export"; 
            width = "16"; 
            direction = "inout"; 
            Is_Enabled = "0"; 
         } 
         PORT zs_dqm 
         { 
            type = "export"; 
            width = "2"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT zs_ras_n 
         { 
            type = "export"; 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
         PORT zs_we_n 
         { 
            type = "export"; 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "0"; 
         } 
      } 
      iss_model_name = "altera_memory"; 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         register_data_in = "1"; 
         sim_model_base = "0"; 
         sdram_data_width = "16"; 
         sdram_addr_width = "13"; 
         sdram_row_width = "13"; 
         sdram_col_width = "9"; 
         sdram_num_chipselects = "1"; 
         sdram_num_banks = "4"; 
         refresh_period = "15.625"; 
         powerup_delay = "100.0"; 
         cas_latency = "3"; 
         t_rfc = "70.0"; 
         t_rp = "20.0"; 
         t_mrd = "3"; 
         t_rcd = "20.0"; 
         t_ac = "5.5"; 
         t_wr = "14.0"; 
         init_refresh_commands = "2"; 
         init_nop_delay = "0.0"; 
         shared_data = "0"; 
         sdram_bank_width = "2"; 
         tristate_bridge_slave = ""; 
         starvation_indicator = "0"; 
         is_initialized = "1"; 
      } 
      SIMULATION  
      { 
         DISPLAY  
         { 
            SIGNAL a 
            { 
               name = "az_addr"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL b 
            { 
               name = "az_be_n"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL c 
            { 
               name = "az_cs"; 
            } 
            SIGNAL d 
            { 
               name = "az_data"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL e 
            { 
               name = "az_rd_n"; 
            } 
            SIGNAL f 
            { 
               name = "az_wr_n"; 
            } 
            SIGNAL h 
            { 
               name = "za_data"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL i 
            { 
               name = "za_valid"; 
            } 
            SIGNAL j 
            { 
               name = "za_waitrequest"; 
            } 
            SIGNAL l 
            { 
               name = "CODE"; 
               radix = "ascii"; 
            } 
            SIGNAL g 
            { 
               name = "clk"; 
            } 
            SIGNAL k 
            { 
               name = "za_cannotrefresh"; 
               suppress = "1"; 
            } 
            SIGNAL m 
            { 
               name = "zs_addr"; 
               radix = "hexadecimal"; 
               suppress = "0"; 
            } 
            SIGNAL n 
            { 
               name = "zs_ba"; 
               radix = "hexadecimal"; 
               suppress = "0"; 
            } 
            SIGNAL o 
            { 
               name = "zs_cs_n"; 
               radix = "hexadecimal"; 
               suppress = "0"; 
            } 
            SIGNAL p 
            { 
               name = "zs_ras_n"; 
               suppress = "0"; 
            } 
            SIGNAL q 
            { 
               name = "zs_cas_n"; 
               suppress = "0"; 
            } 
            SIGNAL r 
            { 
               name = "zs_we_n"; 
               suppress = "0"; 
            } 
            SIGNAL s 
            { 
               name = "zs_dq"; 
               radix = "hexadecimal"; 
               suppress = "0"; 
            } 
            SIGNAL t 
            { 
               name = "zs_dqm"; 
               radix = "hexadecimal"; 
               suppress = "0"; 
            } 
            SIGNAL u 
            { 
               name = "zt_addr"; 
               radix = "hexadecimal"; 
               suppress = "1"; 
            } 
            SIGNAL v 
            { 
               name = "zt_ba"; 
               radix = "hexadecimal"; 
               suppress = "1"; 
            } 
            SIGNAL w 
            { 
               name = "zt_oe"; 
               suppress = "1"; 
            } 
            SIGNAL x 
            { 
               name = "zt_cke"; 
               suppress = "1"; 
            } 
            SIGNAL y 
            { 
               name = "zt_chipselect"; 
               suppress = "1"; 
            } 
            SIGNAL z0 
            { 
               name = "zt_lock_n"; 
               suppress = "1"; 
            } 
            SIGNAL z1 
            { 
               name = "zt_ras_n"; 
               suppress = "1"; 
            } 
            SIGNAL z2 
            { 
               name = "zt_cas_n"; 
               suppress = "1"; 
            } 
            SIGNAL z3 
            { 
               name = "zt_we_n"; 
               suppress = "1"; 
            } 
            SIGNAL z4 
            { 
               name = "zt_cs_n"; 
               radix = "hexadecimal"; 
               suppress = "1"; 
            } 
            SIGNAL z5 
            { 
               name = "zt_dqm"; 
               radix = "hexadecimal"; 
               suppress = "1"; 
            } 
            SIGNAL z6 
            { 
               name = "zt_data"; 
               radix = "hexadecimal"; 
               suppress = "1"; 
            } 
            SIGNAL z7 
            { 
               name = "tz_data"; 
               radix = "hexadecimal"; 
               suppress = "1"; 
            } 
            SIGNAL z8 
            { 
               name = "tz_waitrequest"; 
               suppress = "1"; 
            } 
         } 
         Fix_Me_Up = ""; 
      } 
      SYSTEM_BUILDER_INFO  
      { 
         Instantiate_In_System_Module = "1"; 
         Is_Enabled = "1"; 
         Default_Module_Name = "sdram"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
         Disable_Simulation_Port_Wiring = "0"; 
         View  
         { 
            MESSAGES  
            { 
            } 
            Settings_Summary = "16777216 x 16<br> 
                Memory size: 32 MBytes<br> 
                256 MBits 
                "; 
         } 
      } 
      class = "altera_avalon_new_sdram_controller"; 
      class_version = "7.08110"; 
      HDL_INFO  
      { 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.v"; 
         Synthesis_Only_Files = ""; 
      } 
   } 
   MODULE uart 
   { 
      SLAVE s1 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT irq 
            { 
               type = "irq"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT address 
            { 
               type = "address"; 
               width = "3"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT begintransfer 
            { 
               type = "begintransfer"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT chipselect 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT read_n 
            { 
               type = "read_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT write_n 
            { 
               type = "write_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT writedata 
            { 
               type = "writedata"; 
               width = "16"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT readdata 
            { 
               type = "readdata"; 
               width = "16"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT dataavailable 
            { 
               type = "dataavailable"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT readyfordata 
            { 
               type = "readyfordata"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Has_IRQ = "1"; 
            Bus_Type = "avalon"; 
            Write_Wait_States = "1cycles"; 
            Read_Wait_States = "1cycles"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "1"; 
            Address_Alignment = "native"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "0"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "0"; 
            Maximum_Pending_Read_Transactions = "0"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "0"; 
            Data_Width = "16"; 
            Address_Width = "3"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00001800"; 
            } 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "2"; 
            } 
            Base_Address = "0x00001800"; 
            Address_Group = "0"; 
         } 
      } 
      PORT_WIRING  
      { 
         PORT rxd 
         { 
            type = "export"; 
            width = "1"; 
            direction = "input"; 
            Is_Enabled = "1"; 
         } 
         PORT txd 
         { 
            type = "export"; 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "1"; 
         } 
         PORT cts_n 
         { 
            direction = "input"; 
            width = "1"; 
            Is_Enabled = "0"; 
         } 
         PORT rts_n 
         { 
            direction = "output"; 
            width = "1"; 
            Is_Enabled = "0"; 
         } 
      } 
      class = "altera_avalon_uart"; 
      class_version = "7.08110"; 
      iss_model_name = "altera_avalon_uart"; 
      SYSTEM_BUILDER_INFO  
      { 
         Instantiate_In_System_Module = "1"; 
         Is_Enabled = "1"; 
         Iss_Launch_Telnet = "0"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         View  
         { 
            Settings_Summary = "8-bit UART with 115200 baud, <br> 
                    1 stop bits and N parity"; 
            Is_Collapsed = "1"; 
            MESSAGES  
            { 
            } 
         } 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
      } 
      SIMULATION  
      { 
         DISPLAY  
         { 
            SIGNAL a 
            { 
               name = "  Bus Interface"; 
               format = "Divider"; 
            } 
            SIGNAL b 
            { 
               name = "chipselect"; 
            } 
            SIGNAL c 
            { 
               name = "address"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL d 
            { 
               name = "writedata"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL e 
            { 
               name = "readdata"; 
               radix = "hexadecimal"; 
            } 
            SIGNAL f 
            { 
               name = "  Internals"; 
               format = "Divider"; 
            } 
            SIGNAL g 
            { 
               name = "tx_ready"; 
            } 
            SIGNAL h 
            { 
               name = "tx_data"; 
               radix = "ascii"; 
            } 
            SIGNAL i 
            { 
               name = "rx_char_ready"; 
            } 
            SIGNAL j 
            { 
               name = "rx_data"; 
               radix = "ascii"; 
            } 
         } 
         INTERACTIVE_OUT log 
         { 
            enable = "0"; 
            file = "_log_module.txt"; 
            radix = "ascii"; 
            signals = "temp,list"; 
            exe = "perl -- tail-f.pl"; 
         } 
         INTERACTIVE_IN drive 
         { 
            enable = "0"; 
            file = "_input_data_stream.dat"; 
            mutex = "_input_data_mutex.dat"; 
            log = "_in.log"; 
            rate = "100"; 
            signals = "temp,list"; 
            exe = "perl -- uart.pl"; 
         } 
      } 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         baud = "115200"; 
         data_bits = "8"; 
         fixed_baud = "0"; 
         parity = "N"; 
         stop_bits = "1"; 
         sync_reg_depth = "2"; 
         use_cts_rts = "0"; 
         use_eop_register = "0"; 
         sim_true_baud = "0"; 
         sim_char_stream = ""; 
         relativepath = "1"; 
      } 
      HDL_INFO  
      { 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart.v"; 
         Synthesis_Only_Files = ""; 
      } 
   } 
   MODULE epcs 
   { 
      SLAVE epcs_control_port 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT irq 
            { 
               type = "irq"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT address 
            { 
               type = "address"; 
               width = "9"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT chipselect 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT dataavailable 
            { 
               type = "dataavailable"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT endofpacket 
            { 
               type = "endofpacket"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT read_n 
            { 
               type = "read_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT readdata 
            { 
               type = "readdata"; 
               width = "32"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT readyfordata 
            { 
               type = "readyfordata"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT write_n 
            { 
               type = "write_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT writedata 
            { 
               type = "writedata"; 
               width = "32"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT data_from_cpu 
            { 
               Is_Enabled = "0"; 
               direction = "input"; 
               type = "writedata"; 
               width = "16"; 
            } 
            PORT data_to_cpu 
            { 
               Is_Enabled = "0"; 
               direction = "output"; 
               type = "readdata"; 
               width = "16"; 
            } 
            PORT epcs_select 
            { 
               Is_Enabled = "0"; 
               direction = "input"; 
               type = "chipselect"; 
               width = "1"; 
            } 
            PORT mem_addr 
            { 
               Is_Enabled = "0"; 
               direction = "input"; 
               type = "address"; 
               width = "3"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Has_IRQ = "1"; 
            Bus_Type = "avalon"; 
            Write_Wait_States = "1cycles"; 
            Read_Wait_States = "1cycles"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "0"; 
            Address_Alignment = "dynamic"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "1"; 
            Address_Span = "2048"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "1"; 
            Maximum_Pending_Read_Transactions = "0"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "1"; 
            Data_Width = "32"; 
            Address_Width = "9"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            MASTERED_BY EP2C8/instruction_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00000000"; 
            } 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00000000"; 
            } 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "1"; 
            } 
            Base_Address = "0x00000000"; 
            Address_Group = "0"; 
         } 
         WIZARD_SCRIPT_ARGUMENTS  
         { 
            class = "altera_avalon_epcs_flash_controller"; 
            flash_reference_designator = ""; 
         } 
      } 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         databits = "8"; 
         targetclock = "20"; 
         clockunits = "MHz"; 
         clockmult = "1000000"; 
         numslaves = "1"; 
         ismaster = "1"; 
         clockpolarity = "0"; 
         clockphase = "0"; 
         lsbfirst = "0"; 
         extradelay = "0"; 
         targetssdelay = "100"; 
         delayunits = "us"; 
         delaymult = "1e-006"; 
         prefix = "epcs_"; 
         register_offset = "0x200"; 
         ignore_legacy_check = "1"; 
         use_asmi_atom = "1"; 
         MAKE  
         { 
            MACRO  
            { 
               EPCS_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_BOOT_ROM_FLASHTARGET_TMP1:0=)"; 
               EPCS_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)"; 
            } 
            MASTER EP2C8 
            { 
               MACRO  
               { 
                  BOOTS_FROM_EPCS = "1"; 
                  BOOT_COPIER_EPCS = "boot_loader_epcs.srec"; 
                  CPU_CLASS = "altera_nios2"; 
                  CPU_RESET_ADDRESS = "0x0"; 
               } 
            } 
            TARGET delete_placeholder_warning 
            { 
               epcs  
               { 
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt"; 
                  Is_Phony = "1"; 
                  Target_File = "do_delete_placeholder_warning"; 
               } 
            } 
            TARGET flashfiles 
            { 
               epcs  
               { 
                  Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS)$(DBL_QUOTE) --outfile=$(EPCS_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF  ; fi"; 
                  Dependency = "$(ELF)"; 
                  Target_File = "$(EPCS_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_boot_rom.flash"; 
               } 
            } 
            TARGET sim 
            { 
               epcs  
               { 
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi"; 
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)"; 
                  Command3 = "touch $(SIMDIR)/dummy_file"; 
                  Dependency = "$(ELF)"; 
                  Target_File = "$(SIMDIR)/dummy_file"; 
               } 
            } 
         } 
         clockunit = "kHz"; 
         delayunit = "us"; 
         disableAvalonFlowControl = "0"; 
         insert_sync = "0"; 
         sync_reg_depth = "2"; 
      } 
      class = "altera_avalon_epcs_flash_controller"; 
      class_version = "7.08110"; 
      SYSTEM_BUILDER_INFO  
      { 
         Is_Enabled = "1"; 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
         Instantiate_In_System_Module = "1"; 
         Required_Device_Family = "STRATIX,CYCLONE,CYCLONEII,CYCLONEIII,STRATIXIII,STRATIXII,STRATIXIIGX,ARRIAGX,STRATIXIIGXLITE,STRATIXIV,STRATIXV,ARRIAII,ARRIAIIGZ,TARPON,STINGRAY,CYCLONEIVE"; 
         Fixed_Module_Name = "epcs_controller"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         View  
         { 
            MESSAGES  
            { 
            } 
         } 
      } 
      HDL_INFO  
      { 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs.v"; 
         Synthesis_Only_Files = ""; 
      } 
      PORT_WIRING  
      { 
      } 
   } 
   MODULE TIM2 
   { 
      SLAVE s1 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT irq 
            { 
               type = "irq"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT address 
            { 
               type = "address"; 
               width = "3"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT writedata 
            { 
               type = "writedata"; 
               width = "16"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT readdata 
            { 
               type = "readdata"; 
               width = "16"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT chipselect 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT write_n 
            { 
               type = "write_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Has_IRQ = "1"; 
            Bus_Type = "avalon"; 
            Write_Wait_States = "0cycles"; 
            Read_Wait_States = "1cycles"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "0"; 
            Address_Alignment = "native"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "0"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "0"; 
            Maximum_Pending_Read_Transactions = "0"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "0"; 
            Data_Width = "16"; 
            Address_Width = "3"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00001820"; 
            } 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "4"; 
            } 
            Base_Address = "0x00001820"; 
            Address_Group = "0"; 
         } 
      } 
      class = "altera_avalon_timer"; 
      class_version = "7.08110"; 
      iss_model_name = "altera_avalon_timer"; 
      SYSTEM_BUILDER_INFO  
      { 
         Instantiate_In_System_Module = "1"; 
         Is_Enabled = "1"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         View  
         { 
            Settings_Summary = "Timer with 1 ms timeout period."; 
            Is_Collapsed = "1"; 
            MESSAGES  
            { 
            } 
         } 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
      } 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         always_run = "0"; 
         fixed_period = "0"; 
         snapshot = "1"; 
         period = "1"; 
         period_units = "ms"; 
         reset_output = "0"; 
         timeout_pulse_output = "0"; 
         load_value = "49999"; 
         counter_size = "32"; 
         mult = "0.0010"; 
         ticks_per_sec = "1000"; 
      } 
      HDL_INFO  
      { 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/TIM2.v"; 
         Synthesis_Only_Files = ""; 
      } 
      PORT_WIRING  
      { 
      } 
   } 
   MODULE watchdog 
   { 
      SLAVE s1 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT irq 
            { 
               type = "irq"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT address 
            { 
               type = "address"; 
               width = "3"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT writedata 
            { 
               type = "writedata"; 
               width = "16"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT readdata 
            { 
               type = "readdata"; 
               width = "16"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT chipselect 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT write_n 
            { 
               type = "write_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT resetrequest 
            { 
               type = "resetrequest"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Has_IRQ = "1"; 
            Bus_Type = "avalon"; 
            Write_Wait_States = "0cycles"; 
            Read_Wait_States = "1cycles"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "0"; 
            Address_Alignment = "native"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "0"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "0"; 
            Maximum_Pending_Read_Transactions = "0"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "0"; 
            Data_Width = "16"; 
            Address_Width = "3"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00001840"; 
            } 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "0"; 
            } 
            Base_Address = "0x00001840"; 
            Address_Group = "0"; 
         } 
      } 
      class = "altera_avalon_timer"; 
      class_version = "7.08110"; 
      iss_model_name = "altera_avalon_timer"; 
      SYSTEM_BUILDER_INFO  
      { 
         Instantiate_In_System_Module = "1"; 
         Is_Enabled = "1"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         View  
         { 
            Settings_Summary = "Timer with 40 ms timeout period."; 
            Is_Collapsed = "1"; 
            MESSAGES  
            { 
            } 
         } 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
      } 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         always_run = "1"; 
         fixed_period = "1"; 
         snapshot = "0"; 
         period = "40"; 
         period_units = "ms"; 
         reset_output = "1"; 
         timeout_pulse_output = "0"; 
         load_value = "1999999"; 
         counter_size = "32"; 
         mult = "0.0010"; 
         ticks_per_sec = "25"; 
      } 
      HDL_INFO  
      { 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/watchdog.v"; 
         Synthesis_Only_Files = ""; 
      } 
      PORT_WIRING  
      { 
      } 
   } 
   MODULE SCL 
   { 
      SLAVE s1 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT address 
            { 
               type = "address"; 
               width = "2"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT write_n 
            { 
               type = "write_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT writedata 
            { 
               type = "writedata"; 
               width = "32"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT chipselect 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT readdata 
            { 
               type = "readdata"; 
               width = "32"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Bus_Type = "avalon"; 
            Write_Wait_States = "0cycles"; 
            Read_Wait_States = "1cycles"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "0"; 
            Address_Alignment = "native"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "0"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "0"; 
            Maximum_Pending_Read_Transactions = "0"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "0"; 
            Data_Width = "32"; 
            Address_Width = "2"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00001880"; 
            } 
            Base_Address = "0x00001880"; 
            Has_IRQ = "0"; 
            Address_Group = "0"; 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "NC"; 
            } 
            Is_Readable = "0"; 
            Is_Writable = "1"; 
         } 
      } 
      PORT_WIRING  
      { 
         PORT out_port 
         { 
            type = "export"; 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "1"; 
         } 
         PORT in_port 
         { 
            direction = "input"; 
            Is_Enabled = "0"; 
            width = "32"; 
         } 
         PORT bidir_port 
         { 
            direction = "inout"; 
            Is_Enabled = "0"; 
            width = "32"; 
         } 
      } 
      class = "altera_avalon_pio"; 
      class_version = "7.08110"; 
      SYSTEM_BUILDER_INFO  
      { 
         Is_Enabled = "1"; 
         Instantiate_In_System_Module = "1"; 
         Wire_Test_Bench_Values = "1"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
         Date_Modified = ""; 
         View  
         { 
            MESSAGES  
            { 
            } 
            Settings_Summary = " 32-bit PIO using <br> 
					 
					 
					 output pins"; 
         } 
      } 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         Do_Test_Bench_Wiring = "0"; 
         Driven_Sim_Value = "0"; 
         has_tri = "0"; 
         has_out = "1"; 
         has_in = "0"; 
         capture = "0"; 
         Data_Width = "1"; 
         reset_value = "0"; 
         edge_type = "NONE"; 
         irq_type = "NONE"; 
         bit_clearing_edge_register = "0"; 
         bit_modifying_output_register = "0"; 
      } 
      HDL_INFO  
      { 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SCL.v"; 
         Synthesis_Only_Files = ""; 
      } 
   } 
   MODULE SDA 
   { 
      SLAVE s1 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT address 
            { 
               type = "address"; 
               width = "2"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT write_n 
            { 
               type = "write_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT writedata 
            { 
               type = "writedata"; 
               width = "32"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT chipselect 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT readdata 
            { 
               type = "readdata"; 
               width = "32"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Bus_Type = "avalon"; 
            Write_Wait_States = "0cycles"; 
            Read_Wait_States = "1cycles"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "0"; 
            Address_Alignment = "native"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "0"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "0"; 
            Maximum_Pending_Read_Transactions = "0"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "0"; 
            Data_Width = "32"; 
            Address_Width = "2"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00001890"; 
            } 
            Base_Address = "0x00001890"; 
            Has_IRQ = "0"; 
            Address_Group = "0"; 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "NC"; 
            } 
            Is_Readable = "1"; 
            Is_Writable = "1"; 
         } 
      } 
      PORT_WIRING  
      { 
         PORT bidir_port 
         { 
            type = "export"; 
            width = "1"; 
            direction = "inout"; 
            Is_Enabled = "1"; 
         } 
         PORT in_port 
         { 
            direction = "input"; 
            Is_Enabled = "0"; 
            width = "32"; 
         } 
         PORT out_port 
         { 
            direction = "output"; 
            Is_Enabled = "0"; 
            width = "32"; 
         } 
      } 
      class = "altera_avalon_pio"; 
      class_version = "7.08110"; 
      SYSTEM_BUILDER_INFO  
      { 
         Is_Enabled = "1"; 
         Instantiate_In_System_Module = "1"; 
         Wire_Test_Bench_Values = "1"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
         Date_Modified = ""; 
         View  
         { 
            MESSAGES  
            { 
            } 
            Settings_Summary = " 32-bit PIO using <br> 
					 tri-state pins with edge type NONE and interrupt source NONE 
					 
					"; 
         } 
      } 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         Do_Test_Bench_Wiring = "0"; 
         Driven_Sim_Value = "0"; 
         has_tri = "1"; 
         has_out = "0"; 
         has_in = "0"; 
         capture = "0"; 
         Data_Width = "1"; 
         reset_value = "0"; 
         edge_type = "NONE"; 
         irq_type = "NONE"; 
         bit_clearing_edge_register = "0"; 
         bit_modifying_output_register = "0"; 
      } 
      HDL_INFO  
      { 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SDA.v"; 
         Synthesis_Only_Files = ""; 
      } 
   } 
   MODULE LED 
   { 
      SLAVE s1 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT address 
            { 
               type = "address"; 
               width = "2"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT write_n 
            { 
               type = "write_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT writedata 
            { 
               type = "writedata"; 
               width = "32"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT chipselect 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT readdata 
            { 
               type = "readdata"; 
               width = "32"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Bus_Type = "avalon"; 
            Write_Wait_States = "0cycles"; 
            Read_Wait_States = "1cycles"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "0"; 
            Address_Alignment = "native"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "0"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "0"; 
            Maximum_Pending_Read_Transactions = "0"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "0"; 
            Data_Width = "32"; 
            Address_Width = "2"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x000018a0"; 
            } 
            Base_Address = "0x000018a0"; 
            Has_IRQ = "0"; 
            Address_Group = "0"; 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "NC"; 
            } 
            Is_Readable = "0"; 
            Is_Writable = "1"; 
         } 
      } 
      PORT_WIRING  
      { 
         PORT out_port 
         { 
            type = "export"; 
            width = "1"; 
            direction = "output"; 
            Is_Enabled = "1"; 
         } 
         PORT in_port 
         { 
            direction = "input"; 
            Is_Enabled = "0"; 
            width = "32"; 
         } 
         PORT bidir_port 
         { 
            direction = "inout"; 
            Is_Enabled = "0"; 
            width = "32"; 
         } 
      } 
      class = "altera_avalon_pio"; 
      class_version = "7.08110"; 
      SYSTEM_BUILDER_INFO  
      { 
         Is_Enabled = "1"; 
         Instantiate_In_System_Module = "1"; 
         Wire_Test_Bench_Values = "1"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
         Date_Modified = ""; 
         View  
         { 
            MESSAGES  
            { 
            } 
            Settings_Summary = " 32-bit PIO using <br> 
					 
					 
					 output pins"; 
         } 
      } 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         Do_Test_Bench_Wiring = "0"; 
         Driven_Sim_Value = "0"; 
         has_tri = "0"; 
         has_out = "1"; 
         has_in = "0"; 
         capture = "0"; 
         Data_Width = "1"; 
         reset_value = "0"; 
         edge_type = "NONE"; 
         irq_type = "NONE"; 
         bit_clearing_edge_register = "0"; 
         bit_modifying_output_register = "0"; 
      } 
      HDL_INFO  
      { 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LED.v"; 
         Synthesis_Only_Files = ""; 
      } 
   } 
   MODULE TIM1 
   { 
      SLAVE s1 
      { 
         PORT_WIRING  
         { 
            PORT clk 
            { 
               type = "clk"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT reset_n 
            { 
               type = "reset_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT irq 
            { 
               type = "irq"; 
               width = "1"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT address 
            { 
               type = "address"; 
               width = "3"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT writedata 
            { 
               type = "writedata"; 
               width = "16"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT readdata 
            { 
               type = "readdata"; 
               width = "16"; 
               direction = "output"; 
               Is_Enabled = "1"; 
            } 
            PORT chipselect 
            { 
               type = "chipselect"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
            PORT write_n 
            { 
               type = "write_n"; 
               width = "1"; 
               direction = "input"; 
               Is_Enabled = "1"; 
            } 
         } 
         SYSTEM_BUILDER_INFO  
         { 
            Has_IRQ = "1"; 
            Bus_Type = "avalon"; 
            Write_Wait_States = "0cycles"; 
            Read_Wait_States = "1cycles"; 
            Hold_Time = "0cycles"; 
            Setup_Time = "0cycles"; 
            Is_Printable_Device = "0"; 
            Address_Alignment = "native"; 
            Well_Behaved_Waitrequest = "0"; 
            Is_Nonvolatile_Storage = "0"; 
            Read_Latency = "0"; 
            Is_Memory_Device = "0"; 
            Maximum_Pending_Read_Transactions = "0"; 
            Minimum_Uninterrupted_Run_Length = "1"; 
            Accepts_Internal_Connections = "1"; 
            Write_Latency = "0"; 
            Is_Flash = "0"; 
            Data_Width = "16"; 
            Address_Width = "3"; 
            Maximum_Burst_Size = "1"; 
            Register_Incoming_Signals = "0"; 
            Register_Outgoing_Signals = "0"; 
            Interleave_Bursts = "0"; 
            Linewrap_Bursts = "0"; 
            Burst_On_Burst_Boundaries_Only = "0"; 
            Always_Burst_Max_Burst = "0"; 
            Is_Big_Endian = "0"; 
            Is_Enabled = "1"; 
            MASTERED_BY EP2C8/data_master 
            { 
               priority = "1"; 
               Offset_Address = "0x00001860"; 
            } 
            IRQ_MASTER EP2C8/data_master 
            { 
               IRQ_Number = "3"; 
            } 
            Base_Address = "0x00001860"; 
            Address_Group = "0"; 
         } 
      } 
      class = "altera_avalon_timer"; 
      class_version = "7.08110"; 
      iss_model_name = "altera_avalon_timer"; 
      SYSTEM_BUILDER_INFO  
      { 
         Instantiate_In_System_Module = "1"; 
         Is_Enabled = "1"; 
         Top_Level_Ports_Are_Enumerated = "1"; 
         View  
         { 
            Settings_Summary = "Timer with 1 ms timeout period."; 
            Is_Collapsed = "1"; 
            MESSAGES  
            { 
            } 
         } 
         Clock_Source = "clk_0"; 
         Has_Clock = "1"; 
      } 
      WIZARD_SCRIPT_ARGUMENTS  
      { 
         always_run = "0"; 
         fixed_period = "0"; 
         snapshot = "1"; 
         period = "1"; 
         period_units = "ms"; 
         reset_output = "0"; 
         timeout_pulse_output = "0"; 
         load_value = "49999"; 
         counter_size = "32"; 
         mult = "0.0010"; 
         ticks_per_sec = "1000"; 
      } 
      HDL_INFO  
      { 
         Precompiled_Simulation_Library_Files = ""; 
         Simulation_HDL_Files = ""; 
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/TIM1.v"; 
         Synthesis_Only_Files = ""; 
      } 
      PORT_WIRING  
      { 
      } 
   } 
}