www.pudn.com > MyFCS1.zip > CPU_MyFCS2_log.txt, change:2014-05-04,size:3893b


Altera SOPC Builder Version 11.00 Build 157 
Copyright (c) 1999-2009 Altera Corporation.  All rights reserved. 
 
 
No .sopc_builder configuration file(!) 
# 2014.05.04 16:45:18 (*) mk_custom_sdk starting 
# 2014.05.04 16:45:18 (*) Reading project G:/FPGA_Projects/MyFCS1/CPU_MyFCS2.ptf. 
 
# 2014.05.04 16:45:18 (*) Finding all CPUs 
# 2014.05.04 16:45:18 (*) Finding all available components 
# 2014.05.04 16:45:18 (*) Reading G:/FPGA_Projects/MyFCS1/.sopc_builder/install.ptf 
 
# 2014.05.04 16:45:18 (*) Found 63 components 
 
# 2014.05.04 16:45:19 (*) Finding all peripherals 
 
# 2014.05.04 16:45:19 (*) Finding software components 
 
# 2014.05.04 16:45:19 (*) (Legacy SDK Generation Skipped) 
# 2014.05.04 16:45:19 (*) (All TCL Script Generation Skipped) 
# 2014.05.04 16:45:19 (*) (No Libraries Built) 
# 2014.05.04 16:45:19 (*) (Contents Generation Skipped) 
# 2014.05.04 16:45:19 (*) mk_custom_sdk finishing 
# 2014.05.04 16:45:19 (*) Starting generation for system: CPU_MyFCS2. 
 
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# 2014.05.04 16:45:20 (*) Running Generator Program for EP2C8 
 
# 2014.05.04 16:45:21 (*) Starting Nios II generation 
# 2014.05.04 16:45:21 (*)   Checking for plaintext license. 
# 2014.05.04 16:45:22 (*)   Plaintext license not found. 
# 2014.05.04 16:45:22 (*)   Checking for encrypted license (non-evaluation). 
# 2014.05.04 16:45:22 (*)   Encrypted license found.  SOF will not be time-limited. 
# 2014.05.04 16:45:22 (*)   Getting CPU configuration settings 
Warning: currently assigned JTAG instance ID 0 for EP2C8/jtag_debug_module is shared by FCS_EP2C8.ptf/EP2C8/jtag_debug_module. Reassigned to 1. 
 
# 2014.05.04 16:45:22 (*)   Elaborating CPU configuration settings 
# 2014.05.04 16:45:22 (*)   Creating all objects for CPU 
# 2014.05.04 16:45:22 (*)     Testbench 
# 2014.05.04 16:45:23 (*)     Instruction decoding 
# 2014.05.04 16:45:23 (*)       Instruction fields 
# 2014.05.04 16:45:23 (*)       Instruction decodes 
# 2014.05.04 16:45:24 (*)       Signals for RTL simulation waveforms 
# 2014.05.04 16:45:24 (*)       Instruction controls 
# 2014.05.04 16:45:24 (*)     Pipeline frontend 
# 2014.05.04 16:45:24 (*)     Pipeline backend 
 
# 2014.05.04 16:45:27 (*)   Generating HDL from CPU objects 
# 2014.05.04 16:45:29 (*)   Creating encrypted HDL 
# 2014.05.04 16:45:31 (*) Done Nios II generation 
 
# 2014.05.04 16:45:31 (*) Running Generator Program for sdram 
 
# 2014.05.04 16:45:32 (*) Running Generator Program for uart 
 
# 2014.05.04 16:45:33 (*) Running Generator Program for epcs 
 
# 2014.05.04 16:45:34 (*) Running Generator Program for TIM2 
 
# 2014.05.04 16:45:35 (*) Running Generator Program for watchdog 
 
# 2014.05.04 16:45:36 (*) Running Generator Program for SCL 
 
# 2014.05.04 16:45:36 (*) Running Generator Program for SDA 
 
# 2014.05.04 16:45:37 (*) Running Generator Program for LED 
 
# 2014.05.04 16:45:38 (*) Running Generator Program for TIM1 
 
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# 2014.05.04 16:45:39 (*) Running Test Generator Program for sdram 
 
# 2014.05.04 16:45:39 (*) Making arbitration and system (top) modules. 
 
# 2014.05.04 16:45:43 (*) Generating Quartus symbol for top level: CPU_MyFCS2 
 
# 2014.05.04 16:45:43 (*) Generating Symbol G:/FPGA_Projects/MyFCS1/CPU_MyFCS2.bsf 
 
# 2014.05.04 16:45:43 (*) Creating command-line system-generation script: G:/FPGA_Projects/MyFCS1/CPU_MyFCS2_generation_script 
 
# 2014.05.04 16:45:43 (*) Running setup for HDL simulator: modelsim 
 
 
# 2014.05.04 16:45:43 (*) Completed generation for system: CPU_MyFCS2. 
# 2014.05.04 16:45:43 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED: 
  SOPC Builder database : G:/FPGA_Projects/MyFCS1/CPU_MyFCS2.ptf  
  System HDL Model : G:/FPGA_Projects/MyFCS1/CPU_MyFCS2.v  
  System Generation Script : G:/FPGA_Projects/MyFCS1/CPU_MyFCS2_generation_script  
 
# 2014.05.04 16:45:43 (*) SUCCESS: SYSTEM GENERATION COMPLETED. 
 
 
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